/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
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/*
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* Meson-G12A clock tree IDs
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*
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* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __G12A_CLKC_H
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#define __G12A_CLKC_H
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#define CLKID_SYS_PLL 0
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#define CLKID_FIXED_PLL 1
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#define CLKID_FCLK_DIV2 2
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#define CLKID_FCLK_DIV3 3
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#define CLKID_FCLK_DIV4 4
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#define CLKID_FCLK_DIV5 5
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#define CLKID_FCLK_DIV7 6
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#define CLKID_GP0_PLL 7
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#define CLKID_CLK81 10
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#define CLKID_MPLL0 11
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#define CLKID_MPLL1 12
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#define CLKID_MPLL2 13
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#define CLKID_MPLL3 14
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#define CLKID_DDR 15
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#define CLKID_DOS 16
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#define CLKID_AUDIO_LOCKER 17
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#define CLKID_MIPI_DSI_HOST 18
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#define CLKID_ETH_PHY 19
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#define CLKID_ISA 20
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#define CLKID_PL301 21
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#define CLKID_PERIPHS 22
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#define CLKID_SPICC0 23
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#define CLKID_I2C 24
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#define CLKID_SANA 25
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#define CLKID_SD 26
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#define CLKID_RNG0 27
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#define CLKID_UART0 28
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#define CLKID_SPICC1 29
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#define CLKID_HIU_IFACE 30
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#define CLKID_MIPI_DSI_PHY 31
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#define CLKID_ASSIST_MISC 32
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#define CLKID_SD_EMMC_A 33
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#define CLKID_SD_EMMC_B 34
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#define CLKID_SD_EMMC_C 35
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#define CLKID_AUDIO_CODEC 36
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#define CLKID_AUDIO 37
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#define CLKID_ETH 38
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#define CLKID_DEMUX 39
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#define CLKID_AUDIO_IFIFO 40
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#define CLKID_ADC 41
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#define CLKID_UART1 42
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#define CLKID_G2D 43
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#define CLKID_RESET 44
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#define CLKID_PCIE_COMB 45
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#define CLKID_PARSER 46
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#define CLKID_USB 47
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#define CLKID_PCIE_PHY 48
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#define CLKID_AHB_ARB0 49
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#define CLKID_AHB_DATA_BUS 50
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#define CLKID_AHB_CTRL_BUS 51
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#define CLKID_HTX_HDCP22 52
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#define CLKID_HTX_PCLK 53
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#define CLKID_BT656 54
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#define CLKID_USB1_DDR_BRIDGE 55
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#define CLKID_MMC_PCLK 56
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#define CLKID_UART2 57
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#define CLKID_VPU_INTR 58
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#define CLKID_GIC 59
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#define CLKID_SD_EMMC_A_CLK0 60
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#define CLKID_SD_EMMC_B_CLK0 61
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#define CLKID_SD_EMMC_C_CLK0 62
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#define CLKID_HIFI_PLL 74
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#define CLKID_VCLK2_VENCI0 80
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#define CLKID_VCLK2_VENCI1 81
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#define CLKID_VCLK2_VENCP0 82
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#define CLKID_VCLK2_VENCP1 83
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#define CLKID_VCLK2_VENCT0 84
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#define CLKID_VCLK2_VENCT1 85
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#define CLKID_VCLK2_OTHER 86
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#define CLKID_VCLK2_ENCI 87
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#define CLKID_VCLK2_ENCP 88
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#define CLKID_DAC_CLK 89
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#define CLKID_AOCLK 90
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#define CLKID_IEC958 91
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#define CLKID_ENC480P 92
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#define CLKID_RNG1 93
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#define CLKID_VCLK2_ENCT 94
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#define CLKID_VCLK2_ENCL 95
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#define CLKID_VCLK2_VENCLMMC 96
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#define CLKID_VCLK2_VENCL 97
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#define CLKID_VCLK2_OTHER1 98
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#define CLKID_FCLK_DIV2P5 99
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#define CLKID_DMA 105
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#define CLKID_EFUSE 106
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#define CLKID_ROM_BOOT 107
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#define CLKID_RESET_SEC 108
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#define CLKID_SEC_AHB_APB3 109
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#define CLKID_VPU_0_SEL 110
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#define CLKID_VPU_0 112
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#define CLKID_VPU_1_SEL 113
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#define CLKID_VPU_1 115
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#define CLKID_VPU 116
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#define CLKID_VAPB_0_SEL 117
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#define CLKID_VAPB_0 119
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#define CLKID_VAPB_1_SEL 120
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#define CLKID_VAPB_1 122
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#define CLKID_VAPB_SEL 123
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#define CLKID_VAPB 124
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#define CLKID_HDMI_PLL 128
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#define CLKID_VID_PLL 129
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#define CLKID_VCLK 138
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#define CLKID_VCLK2 139
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#define CLKID_VCLK_DIV1 148
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#define CLKID_VCLK_DIV2 149
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#define CLKID_VCLK_DIV4 150
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#define CLKID_VCLK_DIV6 151
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#define CLKID_VCLK_DIV12 152
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#define CLKID_VCLK2_DIV1 153
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#define CLKID_VCLK2_DIV2 154
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#define CLKID_VCLK2_DIV4 155
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#define CLKID_VCLK2_DIV6 156
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#define CLKID_VCLK2_DIV12 157
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#define CLKID_CTS_ENCI 162
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#define CLKID_CTS_ENCP 163
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#define CLKID_CTS_VDAC 164
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#define CLKID_HDMI_TX 165
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#define CLKID_HDMI 168
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#define CLKID_MALI_0_SEL 169
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#define CLKID_MALI_0 171
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#define CLKID_MALI_1_SEL 172
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#define CLKID_MALI_1 174
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#define CLKID_MALI 175
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#define CLKID_MPLL_50M 177
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#define CLKID_CPU_CLK 187
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#define CLKID_PCIE_PLL 201
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#define CLKID_VDEC_1 204
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#define CLKID_VDEC_HEVC 207
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#define CLKID_VDEC_HEVCF 210
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#define CLKID_TS 212
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#define CLKID_CPUB_CLK 224
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#define CLKID_GP1_PLL 243
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#define CLKID_DSU_CLK 252
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#define CLKID_CPU1_CLK 253
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#define CLKID_CPU2_CLK 254
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#define CLKID_CPU3_CLK 255
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#define CLKID_SPICC0_SCLK 258
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#define CLKID_SPICC1_SCLK 261
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#define CLKID_NNA_AXI_CLK 264
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#define CLKID_NNA_CORE_CLK 267
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#endif /* __G12A_CLKC_H */
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