// SPDX-License-Identifier: GPL-2.0
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/*
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2015, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "ia_css_types.h"
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#include "sh_css_defs.h"
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#ifndef IA_CSS_NO_DEBUG
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#include "ia_css_debug.h"
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#endif
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#include "sh_css_frac.h"
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#include "assert_support.h"
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#include "bh/bh_2/ia_css_bh.host.h"
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#include "ia_css_s3a.host.h"
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const struct ia_css_3a_config default_3a_config = {
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25559,
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32768,
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7209,
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65535,
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0,
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65535,
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{-3344, -6104, -19143, 19143, 6104, 3344, 0},
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{1027, 0, -9219, 16384, -9219, 1027, 0}
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};
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static unsigned int s3a_raw_bit_depth;
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void
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ia_css_s3a_configure(unsigned int raw_bit_depth)
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{
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s3a_raw_bit_depth = raw_bit_depth;
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}
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static void
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ia_css_ae_encode(
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struct sh_css_isp_ae_params *to,
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const struct ia_css_3a_config *from,
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unsigned int size)
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{
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(void)size;
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/* coefficients to calculate Y */
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to->y_coef_r =
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uDIGIT_FITTING(from->ae_y_coef_r, 16, SH_CSS_AE_YCOEF_SHIFT);
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to->y_coef_g =
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uDIGIT_FITTING(from->ae_y_coef_g, 16, SH_CSS_AE_YCOEF_SHIFT);
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to->y_coef_b =
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uDIGIT_FITTING(from->ae_y_coef_b, 16, SH_CSS_AE_YCOEF_SHIFT);
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}
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static void
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ia_css_awb_encode(
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struct sh_css_isp_awb_params *to,
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const struct ia_css_3a_config *from,
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unsigned int size)
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{
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(void)size;
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/* AWB level gate */
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to->lg_high_raw =
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uDIGIT_FITTING(from->awb_lg_high_raw, 16, s3a_raw_bit_depth);
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to->lg_low =
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uDIGIT_FITTING(from->awb_lg_low, 16, SH_CSS_BAYER_BITS);
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to->lg_high =
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uDIGIT_FITTING(from->awb_lg_high, 16, SH_CSS_BAYER_BITS);
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}
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static void
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ia_css_af_encode(
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struct sh_css_isp_af_params *to,
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const struct ia_css_3a_config *from,
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unsigned int size)
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{
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unsigned int i;
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(void)size;
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/* af fir coefficients */
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for (i = 0; i < 7; ++i) {
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to->fir1[i] =
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sDIGIT_FITTING(from->af_fir1_coef[i], 15,
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SH_CSS_AF_FIR_SHIFT);
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to->fir2[i] =
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sDIGIT_FITTING(from->af_fir2_coef[i], 15,
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SH_CSS_AF_FIR_SHIFT);
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}
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}
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void
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ia_css_s3a_encode(
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struct sh_css_isp_s3a_params *to,
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const struct ia_css_3a_config *from,
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unsigned int size)
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{
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(void)size;
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ia_css_ae_encode(&to->ae, from, sizeof(to->ae));
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ia_css_awb_encode(&to->awb, from, sizeof(to->awb));
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ia_css_af_encode(&to->af, from, sizeof(to->af));
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}
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#if 0
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void
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ia_css_process_s3a(
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unsigned int pipe_id,
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const struct ia_css_pipeline_stage *stage,
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struct ia_css_isp_parameters *params)
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{
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short dmem_offset = stage->binary->info->mem_offsets->dmem.s3a;
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assert(params);
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if (dmem_offset >= 0) {
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ia_css_s3a_encode((struct sh_css_isp_s3a_params *)
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&stage->isp_mem_params[IA_CSS_ISP_DMEM0].address[dmem_offset],
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¶ms->s3a_config);
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ia_css_bh_encode((struct sh_css_isp_bh_params *)
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&stage->isp_mem_params[IA_CSS_ISP_DMEM0].address[dmem_offset],
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¶ms->s3a_config);
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params->isp_params_changed = true;
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params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM0] =
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true;
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}
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params->isp_params_changed = true;
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}
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#endif
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#ifndef IA_CSS_NO_DEBUG
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void
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ia_css_ae_dump(
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const struct sh_css_isp_ae_params *ae,
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unsigned int level)
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{
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if (!ae) return;
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"ae_y_coef_r", ae->y_coef_r);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"ae_y_coef_g", ae->y_coef_g);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"ae_y_coef_b", ae->y_coef_b);
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}
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void
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ia_css_awb_dump(
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const struct sh_css_isp_awb_params *awb,
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unsigned int level)
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{
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"awb_lg_high_raw", awb->lg_high_raw);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"awb_lg_low", awb->lg_low);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"awb_lg_high", awb->lg_high);
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}
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void
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ia_css_af_dump(
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const struct sh_css_isp_af_params *af,
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unsigned int level)
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{
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir1[0]", af->fir1[0]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir1[1]", af->fir1[1]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir1[2]", af->fir1[2]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir1[3]", af->fir1[3]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir1[4]", af->fir1[4]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir1[5]", af->fir1[5]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir1[6]", af->fir1[6]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir2[0]", af->fir2[0]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir2[1]", af->fir2[1]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir2[2]", af->fir2[2]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir2[3]", af->fir2[3]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir2[4]", af->fir2[4]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir2[5]", af->fir2[5]);
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ia_css_debug_dtrace(level, "\t%-32s = %d\n",
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"af_fir2[6]", af->fir2[6]);
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}
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void
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ia_css_s3a_dump(
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const struct sh_css_isp_s3a_params *s3a,
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unsigned int level)
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{
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ia_css_debug_dtrace(level, "S3A Support:\n");
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ia_css_ae_dump(&s3a->ae, level);
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ia_css_awb_dump(&s3a->awb, level);
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ia_css_af_dump(&s3a->af, level);
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}
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void
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ia_css_s3a_debug_dtrace(
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const struct ia_css_3a_config *config,
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unsigned int level)
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{
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ia_css_debug_dtrace(level,
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"config.ae_y_coef_r=%d, config.ae_y_coef_g=%d, config.ae_y_coef_b=%d, config.awb_lg_high_raw=%d, config.awb_lg_low=%d, config.awb_lg_high=%d\n",
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config->ae_y_coef_r, config->ae_y_coef_g,
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config->ae_y_coef_b, config->awb_lg_high_raw,
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config->awb_lg_low, config->awb_lg_high);
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}
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#endif
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void
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ia_css_s3a_hmem_decode(
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struct ia_css_3a_statistics *host_stats,
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const struct ia_css_bh_table *hmem_buf)
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{
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#if defined(HAS_NO_HMEM)
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(void)host_stats;
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(void)hmem_buf;
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#else
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struct ia_css_3a_rgby_output *out_ptr;
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int i;
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/* pixel counts(BQ) for 3A area */
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int count_for_3a;
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int sum_r, diff;
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assert(host_stats);
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assert(host_stats->rgby_data);
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assert(hmem_buf);
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count_for_3a = host_stats->grid.width * host_stats->grid.height
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* host_stats->grid.bqs_per_grid_cell
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* host_stats->grid.bqs_per_grid_cell;
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out_ptr = host_stats->rgby_data;
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ia_css_bh_hmem_decode(out_ptr, hmem_buf);
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/* Calculate sum of histogram of R,
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which should not be less than count_for_3a */
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sum_r = 0;
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for (i = 0; i < HMEM_UNIT_SIZE; i++) {
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sum_r += out_ptr[i].r;
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}
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if (sum_r < count_for_3a) {
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/* histogram is invalid */
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return;
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}
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/* Verify for sum of histogram of R/G/B/Y */
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#if 0
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{
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int sum_g = 0;
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int sum_b = 0;
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int sum_y = 0;
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for (i = 0; i < HMEM_UNIT_SIZE; i++) {
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sum_g += out_ptr[i].g;
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sum_b += out_ptr[i].b;
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sum_y += out_ptr[i].y;
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}
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if (sum_g != sum_r || sum_b != sum_r || sum_y != sum_r) {
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/* histogram is invalid */
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return;
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}
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}
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#endif
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/*
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* Limit the histogram area only to 3A area.
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* In DSP, the histogram of 0 is incremented for pixels
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* which are outside of 3A area. That amount should be subtracted here.
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* hist[0] = hist[0] - ((sum of all hist[]) - (pixel count for 3A area))
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*/
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diff = sum_r - count_for_3a;
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out_ptr[0].r -= diff;
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out_ptr[0].g -= diff;
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out_ptr[0].b -= diff;
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out_ptr[0].y -= diff;
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#endif
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}
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void
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ia_css_s3a_dmem_decode(
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struct ia_css_3a_statistics *host_stats,
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const struct ia_css_3a_output *isp_stats)
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{
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int isp_width, host_width, height, i;
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struct ia_css_3a_output *host_ptr;
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assert(host_stats);
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assert(host_stats->data);
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assert(isp_stats);
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isp_width = host_stats->grid.aligned_width;
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host_width = host_stats->grid.width;
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height = host_stats->grid.height;
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host_ptr = host_stats->data;
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/* Getting 3A statistics from DMEM does not involve any
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* transformation (like the VMEM version), we just copy the data
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* using a different output width. */
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for (i = 0; i < height; i++) {
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memcpy(host_ptr, isp_stats, host_width * sizeof(*host_ptr));
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isp_stats += isp_width;
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host_ptr += host_width;
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}
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}
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/* MW: this is an ISP function */
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static inline int
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merge_hi_lo_14(unsigned short hi, unsigned short lo)
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{
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int val = (int)((((unsigned int)hi << 14) & 0xfffc000) |
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((unsigned int)lo & 0x3fff));
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return val;
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}
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void
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ia_css_s3a_vmem_decode(
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struct ia_css_3a_statistics *host_stats,
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const u16 *isp_stats_hi,
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const uint16_t *isp_stats_lo)
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{
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int out_width, out_height, chunk, rest, kmax, y, x, k, elm_start, elm, ofs;
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const u16 *hi, *lo;
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struct ia_css_3a_output *output;
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assert(host_stats);
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assert(host_stats->data);
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assert(isp_stats_hi);
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assert(isp_stats_lo);
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output = host_stats->data;
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out_width = host_stats->grid.width;
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out_height = host_stats->grid.height;
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hi = isp_stats_hi;
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lo = isp_stats_lo;
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chunk = ISP_VEC_NELEMS >> host_stats->grid.deci_factor_log2;
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chunk = max(chunk, 1);
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for (y = 0; y < out_height; y++) {
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elm_start = y * ISP_S3ATBL_HI_LO_STRIDE;
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rest = out_width;
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x = 0;
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while (x < out_width) {
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kmax = (rest > chunk) ? chunk : rest;
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ofs = y * out_width + x;
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elm = elm_start + x * sizeof(*output) / sizeof(int32_t);
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for (k = 0; k < kmax; k++, elm++) {
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output[ofs + k].ae_y = merge_hi_lo_14(
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hi[elm + chunk * 0], lo[elm + chunk * 0]);
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output[ofs + k].awb_cnt = merge_hi_lo_14(
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hi[elm + chunk * 1], lo[elm + chunk * 1]);
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output[ofs + k].awb_gr = merge_hi_lo_14(
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hi[elm + chunk * 2], lo[elm + chunk * 2]);
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output[ofs + k].awb_r = merge_hi_lo_14(
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hi[elm + chunk * 3], lo[elm + chunk * 3]);
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output[ofs + k].awb_b = merge_hi_lo_14(
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hi[elm + chunk * 4], lo[elm + chunk * 4]);
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output[ofs + k].awb_gb = merge_hi_lo_14(
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hi[elm + chunk * 5], lo[elm + chunk * 5]);
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output[ofs + k].af_hpf1 = merge_hi_lo_14(
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hi[elm + chunk * 6], lo[elm + chunk * 6]);
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output[ofs + k].af_hpf2 = merge_hi_lo_14(
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hi[elm + chunk * 7], lo[elm + chunk * 7]);
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}
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x += chunk;
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rest -= chunk;
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}
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}
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}
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