/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#include "coex.h"
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#include "../mac_reg.h"
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#include "hw.h"
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#include "power_saving.h"
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#define MAC_AX_RTK_RATE 5
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#define MAC_AX_BT_MODE_0_3 0
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#define MAC_AX_BT_MODE_2 2
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#define MAC_AX_CSR_DELAY 0
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#define MAC_AX_CSR_PRI_TO 5
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#define MAC_AX_CSR_TRX_TO 4
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#define MAC_AX_CSR_RATE 80
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#define MAC_AX_SB_DRV_MSK 0xFFFFFF
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#define MAC_AX_SB_DRV_SH 0
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#define MAC_AX_SB_FW_MSK 0x7F
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#define MAC_AX_SB_FW_SH 24
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#define R_AX_LTECOEX_STATUS 0x54
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#define B_AX_GNT_BT_RFC_S0_STA BIT(3)
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#define B_AX_GNT_WL_RFC_S0_STA BIT(2)
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#define B_AX_GNT_BT_RFC_S1_STA BIT(5)
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#define B_AX_GNT_WL_RFC_S1_STA BIT(4)
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#define MAC_AX_BTGS1_NOTIFY BIT(0)
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u32 mac_coex_init(struct mac_ax_adapter *adapter,
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struct mac_ax_coex *coex)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
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u8 val;
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u16 val16;
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u32 ret, val32;
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val = MAC_REG_R8(R_AX_GPIO_MUXCFG);
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MAC_REG_W8(R_AX_GPIO_MUXCFG, val | B_AX_ENBT);
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switch (coex->direction) {
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case MAC_AX_COEX_INNER:
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val = MAC_REG_R8(R_AX_GPIO_MUXCFG + 1);
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val = (val & ~BIT(2)) | BIT(1);
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MAC_REG_W8(R_AX_GPIO_MUXCFG + 1, val);
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break;
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case MAC_AX_COEX_OUTPUT:
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val = MAC_REG_R8(R_AX_GPIO_MUXCFG + 1);
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val = val | BIT(1) | BIT(0);
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MAC_REG_W8(R_AX_GPIO_MUXCFG + 1, val);
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break;
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case MAC_AX_COEX_INPUT:
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val = MAC_REG_R8(R_AX_GPIO_MUXCFG + 1);
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val = val & ~(BIT(2) | BIT(1));
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MAC_REG_W8(R_AX_GPIO_MUXCFG + 1, val);
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break;
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default:
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return MACNOITEM;
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}
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#if MAC_AX_FW_REG_OFLD
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if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
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ret = MAC_REG_W_OFLD(R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN,
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1, 0);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("%s: write offload fail %d",
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__func__, ret);
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return ret;
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}
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ret = MAC_REG_W_OFLD(R_AX_BT_COEX_CFG_2,
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B_AX_GNT_BT_BYPASS_PRIORITY,
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1, 0);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("%s: write offload fail %d",
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__func__, ret);
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return ret;
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}
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ret = MAC_REG_W_OFLD(R_AX_CSR_MODE,
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B_AX_WL_ACT_MSK | B_AX_STATIS_BT_EN |
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B_AX_BT_CNT_REST,
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0x4003, 0);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("%s: write offload fail %d",
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__func__, ret);
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return ret;
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}
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ret = MAC_REG_W_OFLD(R_AX_TRXPTCL_RESP_0, B_AX_RSP_CHK_BTCCA,
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0, 0);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("%s: write offload fail %d",
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__func__, ret);
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return ret;
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}
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ret = MAC_REG_W_OFLD(R_AX_CCA_CFG_0,
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B_AX_BTCCA_BRK_TXOP_EN | B_AX_BTCCA_EN,
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1, 0);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("%s: write offload fail %d",
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__func__, ret);
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return ret;
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}
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switch (coex->pta_mode) {
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case MAC_AX_COEX_RTK_MODE:
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val = MAC_REG_R8(R_AX_GPIO_MUXCFG);
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val = SET_CLR_WORD(val, MAC_AX_BT_MODE_0_3,
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B_AX_BTMODE);
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MAC_REG_W8(R_AX_GPIO_MUXCFG, val);
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ret = MAC_REG_W_OFLD(R_AX_TDMA_MODE,
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B_AX_RTK_BT_ENABLE,
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1, 0);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("%s: write offload fail %d",
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__func__, ret);
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return ret;
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}
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ret = MAC_REG_W_OFLD(R_AX_BT_COEX_CFG_5,
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B_AX_BT_RPT_SAMPLE_RATE_MSK <<
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B_AX_BT_RPT_SAMPLE_RATE_SH,
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MAC_AX_RTK_RATE, 1);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("%s: write offload fail %d",
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__func__, ret);
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return ret;
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}
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break;
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case MAC_AX_COEX_CSR_MODE:
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val = MAC_REG_R8(R_AX_GPIO_MUXCFG);
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val = SET_CLR_WORD(val, MAC_AX_BT_MODE_2, B_AX_BTMODE);
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MAC_REG_W8(R_AX_GPIO_MUXCFG, val);
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ret = MAC_REG_W_OFLD(R_AX_CSR_MODE,
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B_AX_BT_PRI_DETECT_TO_MSK <<
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B_AX_BT_PRI_DETECT_TO_SH,
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MAC_AX_CSR_PRI_TO, 0);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("%s: write offload fail %d",
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__func__, ret);
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return ret;
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}
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ret = MAC_REG_W_OFLD(R_AX_CSR_MODE,
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B_AX_BT_TRX_INIT_DETECT_MSK <<
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B_AX_BT_TRX_INIT_DETECT_SH,
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MAC_AX_CSR_TRX_TO, 0);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("%s: write offload fail %d",
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__func__, ret);
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return ret;
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}
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ret = MAC_REG_W_OFLD(R_AX_CSR_MODE,
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B_AX_BT_STAT_DELAY_MSK <<
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B_AX_BT_STAT_DELAY_SH,
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MAC_AX_CSR_DELAY, 0);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("%s: write offload fail %d",
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__func__, ret);
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return ret;
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}
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ret = MAC_REG_W8_OFLD(R_AX_BT_COEX_CFG_2,
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MAC_AX_CSR_RATE, 1);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("%s: write offload fail %d",
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__func__, ret);
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return ret;
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}
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break;
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default:
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return MACNOITEM;
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}
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return ret;
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}
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#endif
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val = MAC_REG_R8(R_AX_BTC_FUNC_EN);
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MAC_REG_W8(R_AX_BTC_FUNC_EN, val | B_AX_PTA_WL_TX_EN);
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val = MAC_REG_R8(R_AX_BT_COEX_CFG_2 + 1);
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MAC_REG_W8(R_AX_BT_COEX_CFG_2 + 1, val | BIT(0));
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val = MAC_REG_R8(R_AX_CSR_MODE);
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MAC_REG_W8(R_AX_CSR_MODE, val | B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK);
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val = MAC_REG_R8(R_AX_CSR_MODE + 2);
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MAC_REG_W8(R_AX_CSR_MODE + 2, val | BIT(0));
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val = MAC_REG_R8(R_AX_TRXPTCL_RESP_0 + 3);
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MAC_REG_W8(R_AX_TRXPTCL_RESP_0 + 3, val & ~BIT(1));
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val16 = MAC_REG_R16(R_AX_CCA_CFG_0);
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val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN;
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MAC_REG_W16(R_AX_CCA_CFG_0, val16);
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ret = mac_read_lte(adapter, R_AX_LTE_SW_CFG_2, &val32);
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if (ret) {
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PLTFM_MSG_ERR("%s: Read LTE fail!\n", __func__);
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return ret;
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}
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val32 = val32 & B_AX_WL_RX_CTRL;
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ret = mac_write_lte(adapter, R_AX_LTE_SW_CFG_2, val32);
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if (ret) {
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PLTFM_MSG_ERR("%s: Write LTE fail!\n", __func__);
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return ret;
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}
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switch (coex->pta_mode) {
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case MAC_AX_COEX_RTK_MODE:
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val = MAC_REG_R8(R_AX_GPIO_MUXCFG);
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val = SET_CLR_WORD(val, MAC_AX_BT_MODE_0_3,
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B_AX_BTMODE);
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MAC_REG_W8(R_AX_GPIO_MUXCFG, val);
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val = MAC_REG_R8(R_AX_TDMA_MODE);
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MAC_REG_W8(R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE);
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val = MAC_REG_R8(R_AX_BT_COEX_CFG_5);
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val = SET_CLR_WORD(val, MAC_AX_RTK_RATE,
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B_AX_BT_RPT_SAMPLE_RATE);
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MAC_REG_W8(R_AX_BT_COEX_CFG_5, val);
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break;
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case MAC_AX_COEX_CSR_MODE:
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val = MAC_REG_R8(R_AX_GPIO_MUXCFG);
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val = SET_CLR_WORD(val, MAC_AX_BT_MODE_2, B_AX_BTMODE);
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MAC_REG_W8(R_AX_GPIO_MUXCFG, val);
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val16 = MAC_REG_R16(R_AX_CSR_MODE);
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val16 = SET_CLR_WORD(val16, MAC_AX_CSR_PRI_TO,
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B_AX_BT_PRI_DETECT_TO);
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val16 = SET_CLR_WORD(val16, MAC_AX_CSR_TRX_TO,
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B_AX_BT_TRX_INIT_DETECT);
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val16 = SET_CLR_WORD(val16, MAC_AX_CSR_DELAY,
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B_AX_BT_STAT_DELAY);
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val16 = val16 | B_AX_ENHANCED_BT;
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MAC_REG_W16(R_AX_CSR_MODE, val16);
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MAC_REG_W8(R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE);
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break;
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default:
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return MACNOITEM;
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}
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return MACSUCCESS;
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}
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u32 mac_get_gnt(struct mac_ax_adapter *adapter, struct mac_ax_coex_gnt *gnt_cfg)
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{
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u32 val, ret, status;
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struct mac_ax_gnt *gnt;
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ret = mac_read_lte(adapter, R_AX_LTE_SW_CFG_1, &val);
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if (ret) {
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PLTFM_MSG_ERR("Read LTE fail!\n");
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return ret;
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}
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ret = mac_read_lte(adapter, R_AX_LTECOEX_STATUS, &status);
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if (ret) {
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PLTFM_MSG_ERR("Read LTE fail!\n");
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return ret;
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}
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gnt = &gnt_cfg->band0;
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gnt->gnt_bt_sw_en = !!(val & B_AX_GNT_BT_RFC_S0_SW_CTRL);
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gnt->gnt_bt = !!(status & B_AX_GNT_BT_RFC_S0_STA);
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gnt->gnt_wl_sw_en = !!(val & B_AX_GNT_WL_RFC_S0_SW_CTRL);
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gnt->gnt_wl = !!(status & B_AX_GNT_WL_RFC_S0_STA);
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gnt = &gnt_cfg->band1;
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gnt->gnt_bt_sw_en = !!(val & B_AX_GNT_BT_RFC_S1_SW_CTRL);
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gnt->gnt_bt = !!(status & B_AX_GNT_BT_RFC_S1_STA);
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gnt->gnt_wl_sw_en = !!(val & B_AX_GNT_WL_RFC_S1_SW_CTRL);
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gnt->gnt_wl = !!(status & B_AX_GNT_WL_RFC_S1_STA);
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return MACSUCCESS;
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}
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u32 mac_cfg_gnt(struct mac_ax_adapter *adapter, struct mac_ax_coex_gnt *gnt_cfg)
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{
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u32 val, ret;
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ret = mac_read_lte(adapter, R_AX_LTE_SW_CFG_1, &val);
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if (ret) {
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PLTFM_MSG_ERR("Read LTE fail!\n");
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return ret;
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}
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val = (gnt_cfg->band0.gnt_bt ? (B_AX_GNT_BT_RFC_S0_SW_VAL |
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B_AX_GNT_BT_BB_S0_SW_VAL) : 0) |
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(gnt_cfg->band0.gnt_bt_sw_en ?
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(B_AX_GNT_BT_RFC_S0_SW_CTRL |
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B_AX_GNT_BT_BB_S0_SW_CTRL) : 0) |
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(gnt_cfg->band0.gnt_wl ? (B_AX_GNT_WL_RFC_S0_SW_VAL |
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B_AX_GNT_WL_BB_S0_SW_VAL) : 0) |
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(gnt_cfg->band0.gnt_wl_sw_en ?
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(B_AX_GNT_WL_RFC_S0_SW_CTRL |
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B_AX_GNT_WL_BB_S0_SW_CTRL) : 0) |
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(gnt_cfg->band1.gnt_bt ? (B_AX_GNT_BT_RFC_S1_SW_VAL |
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B_AX_GNT_BT_BB_S1_SW_VAL) : 0) |
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(gnt_cfg->band1.gnt_bt_sw_en ?
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(B_AX_GNT_BT_RFC_S1_SW_CTRL |
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B_AX_GNT_BT_BB_S1_SW_CTRL) : 0) |
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(gnt_cfg->band1.gnt_wl ? (B_AX_GNT_WL_RFC_S1_SW_VAL |
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B_AX_GNT_WL_BB_S1_SW_VAL) : 0) |
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(gnt_cfg->band1.gnt_wl_sw_en ?
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(B_AX_GNT_WL_RFC_S1_SW_CTRL |
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B_AX_GNT_WL_BB_S1_SW_CTRL) : 0);
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ret = mac_write_lte(adapter, R_AX_LTE_SW_CFG_1, val);
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if (ret) {
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PLTFM_MSG_ERR("Write LTE fail!\n");
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return ret;
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}
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ret = mac_read_lte(adapter, R_AX_LTE_SW_CFG_2, &val);
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if (ret) {
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PLTFM_MSG_ERR("Read LTE fail!\n");
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return ret;
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}
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val = val & B_AX_WL_RX_CTRL ? B_AX_WL_RX_CTRL : 0 |
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((gnt_cfg->band0.gnt_bt_sw_en || gnt_cfg->band1.gnt_bt_sw_en) ?
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(B_AX_GNT_BT_TX_SW_CTRL | B_AX_GNT_BT_RX_SW_CTRL) : 0) |
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((gnt_cfg->band0.gnt_bt || gnt_cfg->band1.gnt_bt) ?
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(B_AX_GNT_BT_TX_SW_VAL | B_AX_GNT_BT_RX_SW_VAL) : 0) |
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((gnt_cfg->band0.gnt_wl_sw_en || gnt_cfg->band1.gnt_wl_sw_en) ?
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(B_AX_GNT_WL_TX_SW_CTRL | B_AX_GNT_WL_RX_SW_CTRL) : 0) |
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((gnt_cfg->band0.gnt_wl || gnt_cfg->band1.gnt_wl) ?
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(B_AX_GNT_WL_TX_SW_VAL | B_AX_GNT_WL_RX_SW_VAL) : 0);
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ret = mac_write_lte(adapter, R_AX_LTE_SW_CFG_2, val);
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if (ret) {
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PLTFM_MSG_ERR("Write LTE fail!\n");
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return ret;
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}
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return MACSUCCESS;
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}
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u32 mac_cfg_plt(struct mac_ax_adapter *adapter, struct mac_ax_plt *plt)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
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u32 reg, ret;
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u16 val;
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ret = check_mac_en(adapter, plt->band, MAC_AX_CMAC_SEL);
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if (ret)
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return ret;
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reg = plt->band == 0 ? R_AX_BT_PLT : R_AX_BT_PLT_C1;
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val = (plt->tx & MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) |
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(plt->tx & MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) |
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(plt->tx & MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) |
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(plt->tx & MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) |
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(plt->rx & MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) |
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(plt->rx & MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) |
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(plt->rx & MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) |
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(plt->rx & MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) |
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(plt->rx || plt->tx ? B_AX_PLT_EN : 0);
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#if MAC_AX_FW_REG_OFLD
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if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
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ret = MAC_REG_W_OFLD((u16)reg,
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B_AX_TX_PLT_GNT_LTE_RX |
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B_AX_TX_PLT_GNT_BT_TX |
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B_AX_TX_PLT_GNT_BT_RX |
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B_AX_TX_PLT_GNT_WL |
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B_AX_RX_PLT_GNT_LTE_RX |
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B_AX_RX_PLT_GNT_BT_TX |
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B_AX_RX_PLT_GNT_BT_RX |
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B_AX_RX_PLT_GNT_WL,
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val, 1);
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if (ret != MACSUCCESS)
|
PLTFM_MSG_ERR("%s: write offload fail %d",
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__func__, ret);
|
|
return ret;
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}
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#endif
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MAC_REG_W16(reg, val);
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return MACSUCCESS;
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}
|
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u32 mac_read_coex_reg(struct mac_ax_adapter *adapter,
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const u32 offset, u32 *val)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
|
if (offset > 0xFF) {
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PLTFM_MSG_ERR("[ERR]offset exceed coex reg\n");
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return MACBADDR;
|
}
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*val = MAC_REG_R32(R_AX_BTC_CFG + offset);
|
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return MACSUCCESS;
|
}
|
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u32 mac_write_coex_reg(struct mac_ax_adapter *adapter,
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const u32 offset, const u32 val)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
|
if (offset > 0xFF) {
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PLTFM_MSG_ERR("[ERR]offset exceed coex reg\n");
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return MACBADDR;
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}
|
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MAC_REG_W32(R_AX_BTC_CFG + offset, val);
|
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return MACSUCCESS;
|
}
|
|
void mac_cfg_sb(struct mac_ax_adapter *adapter, u32 val)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
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u32 fw_sb;
|
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fw_sb = MAC_REG_R32(R_AX_SCOREBOARD);
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fw_sb = GET_FIELD(fw_sb, MAC_AX_SB_FW);
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fw_sb = fw_sb & ~MAC_AX_BTGS1_NOTIFY;
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if (adapter->sm.pwr == MAC_AX_PWR_OFF || _is_in_lps(adapter))
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fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR;
|
else
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fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR;
|
val = GET_FIELD(val, MAC_AX_SB_DRV);
|
val = B_AX_TOGGLE |
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SET_WORD(val, MAC_AX_SB_DRV) |
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SET_WORD(fw_sb, MAC_AX_SB_FW);
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MAC_REG_W32(R_AX_SCOREBOARD, val);
|
}
|
|
u32 mac_cfg_ctrl_path(struct mac_ax_adapter *adapter, u32 wl)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u8 val = MAC_REG_R8(R_AX_SYS_SDIO_CTRL + 3);
|
|
val = wl ? val | BIT(2) : val & ~BIT(2);
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MAC_REG_W8(R_AX_SYS_SDIO_CTRL + 3, val);
|
|
return MACSUCCESS;
|
}
|
|
u32 mac_get_ctrl_path(struct mac_ax_adapter *adapter, u32 *wl)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u8 val = MAC_REG_R8(R_AX_SYS_SDIO_CTRL + 3);
|
|
*wl = !!(val & BIT(2));
|
|
return MACSUCCESS;
|
}
|
|
u32 mac_get_bt_polt_cnt(struct mac_ax_adapter *adapter,
|
struct mac_ax_bt_polt_cnt *cnt)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 offset = cnt->band ? R_AX_BT_PLT_C1 : R_AX_BT_PLT;
|
u8 val;
|
|
cnt->cnt = MAC_REG_R16(offset + 2);
|
|
val = MAC_REG_R8(offset + 1);
|
MAC_REG_W8(offset + 1, val | BIT(1));
|
|
return MACSUCCESS;
|
}
|
|
u32 mac_write_coex_mask(struct mac_ax_adapter *adapter,
|
u32 offset, u32 mask, u32 val)
|
{
|
u32 ret;
|
|
if (offset < R_AX_BTC_CFG || offset > R_AX_LTE_RDATA) {
|
PLTFM_MSG_ERR("[ERR]offset exceed coex reg\n");
|
return MACBADDR;
|
}
|
|
ret = MAC_REG_W_OFLD((u16)offset, mask, val, 1);
|
if (ret) {
|
PLTFM_MSG_ERR("[ERR]%s fail\n", __func__);
|
return ret;
|
}
|
|
return MACSUCCESS;
|
}
|
