/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_RUA_TBL_EX_H__
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#define __HALBB_RUA_TBL_EX_H__
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#ifdef HALBB_RUA_SUPPORT
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/*@--------------------------[Define] ---------------------------------------*/
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#define HALBB_AX4RU_STA_NUM 4
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#define HALBB_AX8RU_STA_NUM 8
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/*@--------------------------[Enum]------------------------------------------*/
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enum rtw_rua_tbl_hdr_rw {
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RUA_TBL_RW_READ = 0,
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RUA_TBL_RW_WRITE = 1
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};
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enum rtw_rua_tbl_hdr_type {
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RUA_TBL_TYPE_SW = 0,
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RUA_TBL_TYPE_HW = 1
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};
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enum rtw_rua_tbl_hdr_class {
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RUA_TBL_CL_DLRU_SW = 0x0,
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RUA_TBL_CL_ULRU_SW = 0x1,
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RUA_TBL_CL_RU_STA = 0x2,
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RUA_TBL_CL_DLRU_SW_FIX = 0x3,
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RUA_TBL_CL_ULRU_SW_FIX = 0x4,
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RUA_TBL_CL_BA_INFO = 0x5
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};
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/*@--------------------------[Structure]-------------------------------------*/
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struct rtw_rua_tbl_hdr {
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u8 rw:1;
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u8 idx:7;
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u16 offset:5;
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u16 len:10;
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u16 type:1;
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u8 tbl_class;
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};
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struct rtw_ru_rate_ent {
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u8 dcm:1;
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u8 ss:3;
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u8 mcs:4;
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};
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struct rtw_tf_ba_tbl {
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u32 fix_ba:1;
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u32 ru_psd:9;
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u32 tf_rate:9;
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u32 rf_gain_fix:1;
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u32 rf_gain_idx:10;
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u32 tb_ppdu_bw:2;
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struct rtw_ru_rate_ent rate;
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u8 gi_ltf:3;
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u8 doppler:1;
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u8 stbc:1;
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u8 sta_coding:1;
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u8 tb_t_pe_nom:2;
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u8 pr20_bw_en:1;
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u8 ma_type:1;
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u8 rsvd1:6;
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u8 rsvd2;
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};
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struct rtw_dl_ru_gp_tbl {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u16 ppdu_bw:2;
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u16 tx_pwr:9;
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u16 pwr_boost_fac:5;
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u8 fix_mode_flag:1;
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u8 rsvd1:7;
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u8 rsvd2;
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struct rtw_tf_ba_tbl tf;
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};
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struct rtw_ul_ru_gp_tbl {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u32 grp_psd_max:9;
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u32 grp_psd_min:9;
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u32 tf_rate:9;
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u32 fix_tf_rate:1;
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u32 rsvd2:4;
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u16 ppdu_bw:2;
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u16 rf_gain_fix:1;
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u16 rf_gain_idx:10;
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u16 fix_mode_flag:1;
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u16 rsvd1:2;
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};
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struct rtw_ru_sta_info {
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struct rtw_rua_tbl_hdr tbl_hdr;
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/* sta capability */
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u8 gi_ltf_48spt:1;
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u8 gi_ltf_18spt:1;
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u8 rsvd0:6;
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/* dl su */
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u8 dlsu_info_en:1;
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u8 dlsu_bw:2;
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u8 dlsu_gi_ltf:3;
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u8 dlsu_doppler_ctrl:2;
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u8 dlsu_coding:1;
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u8 dlsu_txbf:1;
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u8 dlsu_stbc:1;
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u8 dl_fwcqi_flag:1;
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u8 dlru_ratetbl_ridx:4;
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u8 csi_info_bitmap;
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u32 dl_swgrp_bitmap;
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u16 dlsu_dcm:1;
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u16 rsvd1:6;
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u16 dlsu_rate:9;
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u8 dlsu_pwr:6;
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u8 rsvd2:2;
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u8 rsvd4;
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/* ul su */
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u8 ulsu_info_en:1;
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u8 ulsu_bw:2;
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u8 ulsu_gi_ltf:3;
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u8 ulsu_doppler_ctrl:2;
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u8 ulsu_dcm:1;
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u8 ulsu_ss:3;
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u8 ulsu_mcs:4;
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u16 ul_fwcqi_flag:1;
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u16 ulru_ratetbl_ridx:4;
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u16 ulsu_stbc:1;
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u16 ulsu_coding:1;
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u16 ulsu_rssi_m:9;
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u32 ul_swgrp_bitmap;
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/* tb info */
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};
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/*
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struct rtw_dl_fix_sta_ent {
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u8 mac_id;
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u8 ru_pos[3];
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u8 fix_rate:1;
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u8 fix_coding:1;
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u8 fix_txbf:1;
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u8 fix_pwr_fac:1;
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u8 rsvd0:4;
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struct rtw_ru_rate_ent rate;
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u8 txbf:1;
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u8 coding:1;
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u8 pwr_boost_fac:5;
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u8 rsvd1: 1;
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u8 rsvd2;
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};
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struct rtw_dl_ru_fix_tbl {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 max_sta_num:3;
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u8 min_sta_num:3;
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u8 ru_swp_flg:1;
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u8 rsvd0:1;
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u8 doppler:1;
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u8 stbc:1;
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u8 gi_ltf:3;
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u8 ma_type:1;
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u8 fixru_flag:1;
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u8 rupos_csht_flag:1;
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u8 rsvd2;
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struct rtw_dl_fix_sta_ent sta[HALBB_AX4RU_STA_NUM];
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};
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*/
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struct rtw_dlfix_sta_i_ax4ru {
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u8 mac_id;
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u8 ru_pos[3];
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u8 fix_rate:1;
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u8 fix_coding:1;
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u8 fix_txbf:1;
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u8 fix_pwr_fac:1;
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u8 rsvd0:4;
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struct rtw_ru_rate_ent rate;
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u8 txbf:1;
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u8 coding:1;
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u8 pwr_boost_fac:5;
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u8 rsvd1: 1;
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u8 rsvd2;
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};
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struct rtw_dlru_fixtbl_ax4ru {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 max_sta_num:3;
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u8 min_sta_num:3;
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u8 ru_swp_flg:1;
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u8 rsvd0:1;
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u8 doppler:1;
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u8 stbc:1;
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u8 gi_ltf:3;
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u8 ma_type:1;
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u8 fixru_flag:1;
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u8 rupos_csht_flag:1;
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u8 rsvd2;
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struct rtw_dlfix_sta_i_ax4ru sta[HALBB_AX4RU_STA_NUM];
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};
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union rtw_dlru_fixtbl{
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struct rtw_dlru_fixtbl_ax4ru ax4ru;
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};
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/*
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struct rtw_ul_fix_sta_ent {
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u8 mac_id;
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u8 ru_pos[3];
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u8 tgt_rssi[3];
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u8 fix_tgt_rssi:1;
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u8 fix_rate:1;
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u8 fix_coding:1;
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u8 coding:1;
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u8 rsvd1:4;
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struct rtw_ru_rate_ent rate;
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};
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struct rtw_ul_ru_fix_tbl {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 max_sta_num:3;
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u8 min_sta_num:3;
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u8 doppler:1;
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u8 ma_type:1;
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u8 gi_ltf:3;
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u8 stbc:1;
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u8 fix_tb_t_pe_nom: 1;
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u8 tb_t_pe_nom: 2;
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u8 fixru_flag: 1;
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struct rtw_ul_fix_sta_ent sta[HALBB_AX4RU_STA_NUM];
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};
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*/
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struct rtw_ulfix_sta_i_ax4ru {
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u8 mac_id;
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u8 ru_pos[3];
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u8 tgt_rssi[3];
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u8 fix_tgt_rssi:1;
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u8 fix_rate:1;
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u8 fix_coding:1;
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u8 coding:1;
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u8 rsvd1:4;
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struct rtw_ru_rate_ent rate;
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};
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struct rtw_ulru_fixtbl_ax4ru {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 max_sta_num:3;
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u8 min_sta_num:3;
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u8 doppler:1;
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u8 ma_type:1;
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u8 gi_ltf:3;
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u8 stbc:1;
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u8 fix_tb_t_pe_nom: 1;
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u8 tb_t_pe_nom: 2;
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u8 fixru_flag: 1;
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struct rtw_ulfix_sta_i_ax4ru sta[HALBB_AX4RU_STA_NUM];
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};
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union rtw_ulru_fixtbl{
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struct rtw_ulru_fixtbl_ax4ru ax4ru;
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};
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struct rtw_ba_tbl_info {
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struct rtw_rua_tbl_hdr tbl_hdr;
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struct rtw_tf_ba_tbl tf_ba_t;
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};
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struct rtw_sw_grp_bitmap {
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u8 macid;
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u8 en_upd_dl_swgrp:1;
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u8 en_upd_ul_swgrp:1;
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u8 cmdend:1; // add for determine whether last user or not
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u8 rsvd1:5;
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u32 dl_sw_grp_bitmap;
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u32 ul_sw_grp_bitmap;
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};
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struct rtw_sw_grp_set {
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struct rtw_sw_grp_bitmap swgrp_bitmap[8];
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};
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struct rtw_dl_macid_cfg {
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u32 macid: 8;
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u32 dl_su_rate_cfg: 1;
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u32 dl_su_rate: 9;
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u32 dl_su_bw: 2;
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u32 dl_su_pwr_cfg: 1;
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u32 dl_su_pwr: 6;
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u32 rsvd0: 5;
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u32 gi_ltf_4x8_support: 1;
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u32 gi_ltf_1x8_support: 1;
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u32 rsvd1: 6;
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u32 dl_su_info_en: 1;
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u32 rsvd2: 2;
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u32 dl_su_gi_ltf: 3;
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u32 dl_su_doppler_ctrl: 2;
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u32 dl_su_coding: 1;
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u32 dl_su_txbf: 1;
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u32 dl_su_stbc: 1;
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u32 dl_su_dcm: 1;
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u32 rsvd3: 12;
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};
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struct rtw_ul_macid_cfg {
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u32 macid: 8;
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u32 endcmd: 1;
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u32 rsvd0: 23;
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u32 ul_su_info_en: 1;
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u32 ul_su_bw: 2;
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u32 ul_su_gi_ltf: 3;
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u32 ul_su_doppler_ctrl: 2;
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u32 ul_su_dcm: 1;
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u32 ul_su_ss: 3;
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u32 ul_su_mcs: 4;
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u32 rsvd2: 5;
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u32 ul_su_stbc: 1;
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u32 ul_su_coding: 1;
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u32 ul_su_rssi_m: 9;
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};
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struct rtw_ul_macid_set {
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struct rtw_ul_macid_cfg ul_macid_cfg[8];
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};
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struct rtw_csiinfo_cfg {
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u32 macid: 8;
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u32 csi_info_bitmap: 8;
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u32 rsvd0: 16;
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};
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struct rtw_cqi_info {
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u32 macid: 8;
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u32 fw_cqi_flag: 1; /* UL or DL*/
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u32 ru_rate_table_row_idx: 4; /* UL or DL*/
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u32 ul_dl: 1; /*1'b0 means UL, 1'b1 means DL */
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u32 endcmd: 1;
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u32 rsvd0: 1;
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u32 rsvd1: 16;
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s8 cqi_diff_table[19]; /* UL or DL*/
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u8 rsvd2;
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};
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struct rtw_cqi_set{
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struct rtw_cqi_info cqi_info[8];
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};
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struct rtw_bbinfo_cfg {
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u32 p20_ch_bitmap: 8;
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u32 rsvd0: 24;
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};
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struct rtw_pwr_by_rt_tbl{
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s16 pwr_by_rt[32];
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};
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/*@--------------------------[Prptotype]-------------------------------------*/
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struct bb_info;
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// u32 halbb_upd_dlru_fixtbl(struct bb_info *bb,
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// struct rtw_dl_ru_fix_tbl *info);
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u32 halbb_upd_dlru_fixtbl(struct bb_info *bb,
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union rtw_dlru_fixtbl *union_info);
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u32 halbb_upd_dlru_grptbl(struct bb_info *bb,
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struct rtw_dl_ru_gp_tbl *info);
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// u32 halbb_upd_ulru_fixtbl(struct bb_info *bb,
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// struct rtw_ul_ru_fix_tbl *info);
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u32 halbb_upd_ulru_fixtbl(struct bb_info *bb,
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union rtw_ulru_fixtbl *union_info);
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u32 halbb_upd_ulru_grptbl(struct bb_info *bb,
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struct rtw_ul_ru_gp_tbl *info);
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u32 halbb_upd_rusta_info(struct bb_info *bb,
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struct rtw_ru_sta_info *info);
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u32 halbb_upd_ba_infotbl(struct bb_info *bb,
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struct rtw_ba_tbl_info *info);
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u32 halbb_swgrp_hdl(struct bb_info *bb,
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struct rtw_sw_grp_set *info);
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u32 halbb_dlmacid_cfg(struct bb_info *bb, struct rtw_dl_macid_cfg *cfg);
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u32 halbb_ulmacid_cfg(struct bb_info *bb, struct rtw_ul_macid_set *cfg);
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u32 halbb_csiinfo_cfg(struct bb_info *bb, struct rtw_csiinfo_cfg *cfg);
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u32 halbb_cqi_cfg(struct bb_info *bb, struct rtw_cqi_set *cfg);
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u32 halbb_bbinfo_cfg(struct bb_info *bb, struct rtw_bbinfo_cfg *cfg);
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u32 halbb_pbr_tbl_cfg(struct bb_info *bb, struct rtw_pwr_by_rt_tbl *cfg);
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/*u32 halbb_rua_tbl_init(struct bb_info *bb);*/
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#endif
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#endif
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