/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef _HALBB_PLCP_TX_EX_H_
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#define _HALBB_PLCP_TX_EX_H_
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/* ============================================================
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define
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============================================================
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*/
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#define N_USER 4
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#define DL_STA_LIST_MAX_NUM 8
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/* ============================================================
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Enumeration
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============================================================
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*/
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enum plcp_sts {
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PLCP_SUCCESS = 0,
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LENGTH_EXCEED,
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CCK_INVALID,
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OFDM_INVALID,
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HT_INVALID,
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VHT_INVALID,
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HE_INVALID,
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SPEC_INVALID
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};
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/* ============================================================
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structure
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============================================================
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*/
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struct cr_address_t {
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u32 address;
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u32 bitmask;
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};
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struct ru_rate_entry {
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u8 dcm: 1;
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u8 ss: 3;
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u8 mcs: 4;
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};
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struct rura_report {
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u8 rate_table_col_idx: 6;
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u8 partial_allocation_flag: 1;
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u8 rate_change_flag: 1;
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};
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struct dl_ru_output_sta_entry {
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u8 dropping_flag: 1; //0
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u8 txbf: 1;
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u8 coding: 1;
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u8 nsts: 3;
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u8 rsvd0: 2;
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u8 mac_id: 8;
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u8 ru_position: 8;
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u8 vip_flag: 1; //dont care
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u8 pwr_boost_factor: 5; //dont care
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u8 rsvd1: 2;
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u32 tx_length;
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struct ru_rate_entry ru_rate;
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//for dl rura
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struct rura_report ru_ra_report;
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};
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struct dl_rua_output {
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u16 ru2su_flag: 1;
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u16 ppdu_bw: 2; //set
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u16 group_tx_pwr: 9;
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u16 stbc: 1;
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u16 gi_ltf: 3;
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u8 doppler: 1;
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u8 n_ltf_and_ma: 3;
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u8 sta_list_num: 4; //set
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u8 grp_mode: 1;
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u8 group_id: 6;
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u8 fixed_mode: 1; //set 1
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struct dl_ru_output_sta_entry dl_output_sta_list[DL_STA_LIST_MAX_NUM];
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};
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//sig-b output
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struct sigb_compute_output {
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u8 sta_0_idx: 2;
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u8 sta_1_idx: 2;
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u8 sta_2_idx: 2;
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u8 sta_3_idx: 2;
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u32 hw_sigb_content_channelone_len: 8;
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u32 hw_sigb_content_channeltwo_len: 8;
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u32 hw_sigb_symbolnum: 6;
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u32 hw_sigb_content_channeltwo_offset: 5; //have to +1
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u32 ru2su_flag: 1;
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u32 sigb_dcm: 1;
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u32 sigb_mcs: 3;
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};
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struct bb_h2c_he_sigb {
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u16 aid12[4];
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u8 force_sigb_rate;
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u8 force_sigb_mcs;
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u8 force_sigb_dcm;
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u8 rsvd;
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struct dl_rua_output dl_rua_out;
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struct sigb_compute_output sigb_output;
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struct cr_address_t n_sym_sigb_ch1[16];
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struct cr_address_t n_sym_sigb_ch2[16];
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};
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//========== [Outer-Input] ==========//
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struct usr_plcp_gen_in {
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u32 mcs : 6;
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u32 mpdu_len : 14;
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u32 n_mpdu : 9;
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u32 fec : 1;
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u32 dcm : 1;
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u32 rsvd0 : 1;
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u32 aid : 12;
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u32 scrambler_seed : 8; // rand (1~255)
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u32 random_init_seed : 8; // rand (1~255)
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u32 rsvd1 : 4;
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u32 apep : 22;
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u32 ru_alloc : 8;
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u32 rsvd2 : 2;
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u32 nss : 4;
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u32 txbf : 1;
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u32 pwr_boost_db : 5;
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u32 rsvd3 : 22;
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};
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struct halbb_plcp_info {
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u32 dbw : 2; //0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80
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u32 source_gen_mode : 2;
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u32 locked_clk : 1;
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u32 dyn_bw : 1;
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u32 ndp_en : 1;
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u32 long_preamble_en : 1; //bmode
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u32 stbc : 1;
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u32 gi : 2; //0:0.4,1:0.8,2:1.6,3:3.2
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u32 tb_l_len : 12;
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u32 tb_ru_tot_sts_max : 3;
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u32 vht_txop_not_allowed : 1;
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u32 tb_disam : 1;
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u32 doppler : 2;
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u32 he_ltf_type : 2;//0:1x,1:2x,2:4x
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u32 ht_l_len : 12;
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u32 preamble_puncture : 1;
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u32 he_mcs_sigb : 3;//0~5
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u32 he_dcm_sigb : 1;
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u32 he_sigb_compress_en : 1;
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u32 max_tx_time_0p4us : 14;
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u32 ul_flag : 1;
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u32 tb_ldpc_extra : 1;
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u32 bss_color : 6;
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u32 sr : 4;
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u32 beamchange_en : 1;
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u32 he_er_u106ru_en : 1;
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u32 ul_srp1 : 4;
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u32 ul_srp2 : 4;
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u32 ul_srp3 : 4;
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u32 ul_srp4 : 4;
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u32 mode : 2;
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u32 group_id : 6;
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u32 ppdu_type : 4;//0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB
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u32 txop : 7;
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u32 tb_strt_sts : 3;
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u32 tb_pre_fec_padding_factor : 2;
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u32 cbw : 2;
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u32 txsc : 4;
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u32 tb_mumimo_mode_en : 1;
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u32 rsvd1 : 3;
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u8 nominal_t_pe : 2; // def = 2
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u8 ness : 2; // def = 0
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u8 rsvd2 : 4;
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u8 n_user;
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u16 tb_rsvd : 9;//def = 0
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u16 rsvd3 : 7;
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struct usr_plcp_gen_in usr[N_USER];
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};
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/* ============================================================
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Function Prototype
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============================================================
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*/
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struct bb_info;
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enum plcp_sts halbb_plcp_gen(struct bb_info *bb, struct halbb_plcp_info *in,
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struct usr_plcp_gen_in *user, enum phl_phy_idx phy_idx);
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#endif
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