/** @file mlan_sdio.h
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*
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* @brief This file contains definitions for SDIO interface.
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* driver.
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*
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* Copyright (C) 2008-2017, Marvell International Ltd.
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*
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* This software file (the "File") is distributed by Marvell International
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* Ltd. under the terms of the GNU General Public License Version 2, June 1991
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* (the "License"). You may use, redistribute and/or modify this File in
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* accordance with the terms and conditions of the License, a copy of which
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* is available by writing to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
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* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
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*
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
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* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
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* this warranty disclaimer.
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*
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*/
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/****************************************************
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Change log:
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****************************************************/
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#ifndef _MLAN_SDIO_H
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#define _MLAN_SDIO_H
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/** Block mode */
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#ifndef BLOCK_MODE
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#define BLOCK_MODE 1
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#endif
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/** Fixed address mode */
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#ifndef FIXED_ADDRESS
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#define FIXED_ADDRESS 0
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#endif
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/* Host Control Registers */
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/** Host Control Registers : Host to Card Event */
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#define HOST_TO_CARD_EVENT_REG 0x00
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/** Host Control Registers : Host terminates Command 53 */
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#define HOST_TERM_CMD53 (0x1U << 2)
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/** Host Control Registers : Host without Command 53 finish host */
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#define HOST_WO_CMD53_FINISH_HOST (0x1U << 2)
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/** Host Control Registers : Host power up */
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#define HOST_POWER_UP (0x1U << 1)
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/** Host Control Registers : Host power down */
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#define HOST_POWER_DOWN (0x1U << 0)
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/** Host Control Registers : Host interrupt RSR */
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#define HOST_INT_RSR_REG 0x04
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/** Host Control Registers : Upload host interrupt RSR */
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#define UP_LD_HOST_INT_RSR (0x1U)
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#define HOST_INT_RSR_MASK 0xFF
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/** Host Control Registers : Host interrupt mask */
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#define HOST_INT_MASK_REG 0x08
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/** Host Control Registers : Upload host interrupt mask */
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#define UP_LD_HOST_INT_MASK (0x1U)
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/** Host Control Registers : Download host interrupt mask */
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#define DN_LD_HOST_INT_MASK (0x2U)
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/** Host Control Registers : Cmd port upload interrupt mask */
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#define CMD_PORT_UPLD_INT_MASK (0x1U << 6)
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/** Host Control Registers : Cmd port download interrupt mask */
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#define CMD_PORT_DNLD_INT_MASK (0x1U << 7)
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/** Enable Host interrupt mask */
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#define HIM_ENABLE (UP_LD_HOST_INT_MASK | \
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DN_LD_HOST_INT_MASK | \
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CMD_PORT_UPLD_INT_MASK | \
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CMD_PORT_DNLD_INT_MASK)
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/** Disable Host interrupt mask */
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#define HIM_DISABLE 0xff
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/** Host Control Registers : Host interrupt status */
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#define HOST_INT_STATUS_REG 0x0C
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/** Host Control Registers : Upload command port host interrupt status */
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#define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
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/** Host Control Registers : Download command port host interrupt status */
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#define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
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/** Host Control Registers : Upload host interrupt status */
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#define UP_LD_HOST_INT_STATUS (0x1U)
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/** Host Control Registers : Download host interrupt status */
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#define DN_LD_HOST_INT_STATUS (0x2U)
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/** Port for registers */
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#define REG_PORT 0
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/** Port for memory */
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#define MEM_PORT 0x10000
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/** LSB of read bitmap */
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#define RD_BITMAP_L 0x10
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/** MSB of read bitmap */
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#define RD_BITMAP_U 0x11
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/** LSB of read bitmap second word */
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#define RD_BITMAP_1L 0x12
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/** MSB of read bitmap second word */
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#define RD_BITMAP_1U 0x13
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/** LSB of write bitmap */
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#define WR_BITMAP_L 0x14
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/** MSB of write bitmap */
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#define WR_BITMAP_U 0x15
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/** LSB of write bitmap second word */
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#define WR_BITMAP_1L 0x16
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/** MSB of write bitmap second word */
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#define WR_BITMAP_1U 0x17
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/** LSB of read length for port 0 */
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#define RD_LEN_P0_L 0x18
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/** MSB of read length for port 0 */
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#define RD_LEN_P0_U 0x19
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/* Card Control Registers : Command port read length 0 */
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#define CMD_RD_LEN_0 0xC0
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/* Card Control Registers : Command port read length 1 */
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#define CMD_RD_LEN_1 0xC1
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/* Card Control Registers : Command port read length 2 (reserved) */
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#define CMD_RD_LEN_2 0xC2
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/* Card Control Registers : Command port read length 3 */
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#define CMD_RD_LEN_3 0xC3
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/* Card Control Registers : Command port configuration 0 */
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#define CMD_CONFIG_0 0xC4
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#define CMD_PORT_RD_LEN_EN (0x1U << 2)
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/* Card Control Registers : Command port configuration 1 */
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#define CMD_CONFIG_1 0xC5
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/* Card Control Registers : cmd port auto enable */
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#define CMD_PORT_AUTO_EN (0x1U << 0)
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/* Card Control Registers : Command port configuration 2 (reserved) */
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#define CMD_CONFIG_2 0xC6
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/* Card Control Registers : Command port configuration 3 (reserved) */
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#define CMD_CONFIG_3 0xC7
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/* Command port */
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#define CMD_PORT_SLCT 0x8000
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/** Data port mask */
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#define DATA_PORT_MASK 0xffffffff
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/** Misc. Config Register : Auto Re-enable interrupts */
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#define AUTO_RE_ENABLE_INT MBIT(4)
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/** Host Control Registers : Host transfer status */
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#define HOST_RESTART_REG 0x58
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/** Host Control Registers : Download CRC error */
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#define DN_LD_CRC_ERR (0x1U << 2)
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/** Host Control Registers : Upload restart */
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#define UP_LD_RESTART (0x1U << 1)
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/** Host Control Registers : Download restart */
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#define DN_LD_RESTART (0x1U << 0)
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/* Card Control Registers */
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/** Card Control Registers : Card to host event */
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#define CARD_TO_HOST_EVENT_REG 0x5C
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/** Card Control Registers : Command port upload ready */
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#define UP_LD_CP_RDY (0x1U << 6)
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/** Card Control Registers : Command port download ready */
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#define DN_LD_CP_RDY (0x1U << 7)
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/** Card Control Registers : Card I/O ready */
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#define CARD_IO_READY (0x1U << 3)
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/** Card Control Registers : CIS card ready */
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#define CIS_CARD_RDY (0x1U << 2)
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/** Card Control Registers : Upload card ready */
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#define UP_LD_CARD_RDY (0x1U << 1)
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/** Card Control Registers : Download card ready */
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#define DN_LD_CARD_RDY (0x1U << 0)
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/** Card Control Registers : Host interrupt mask register */
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#define HOST_INTERRUPT_MASK_REG 0x60
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/** Card Control Registers : Host power interrupt mask */
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#define HOST_POWER_INT_MASK (0x1U << 3)
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/** Card Control Registers : Abort card interrupt mask */
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#define ABORT_CARD_INT_MASK (0x1U << 2)
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/** Card Control Registers : Upload card interrupt mask */
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#define UP_LD_CARD_INT_MASK (0x1U << 1)
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/** Card Control Registers : Download card interrupt mask */
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#define DN_LD_CARD_INT_MASK (0x1U << 0)
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/** Card Control Registers : Card interrupt status register */
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#define CARD_INTERRUPT_STATUS_REG 0x64
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/** Card Control Registers : Power up interrupt */
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#define POWER_UP_INT (0x1U << 4)
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/** Card Control Registers : Power down interrupt */
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#define POWER_DOWN_INT (0x1U << 3)
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/** Card Control Registers : Card interrupt RSR register */
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#define CARD_INTERRUPT_RSR_REG 0x68
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/** Card Control Registers : Power up RSR */
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#define POWER_UP_RSR (0x1U << 4)
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/** Card Control Registers : Power down RSR */
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#define POWER_DOWN_RSR (0x1U << 3)
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/** Card Control Registers : SQ Read base address 0 register */
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#define READ_BASE_0_REG 0xf8
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/** Card Control Registers : SQ Read base address 1 register */
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#define READ_BASE_1_REG 0xf9
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/** Enable GPIO-1 as a duplicated signal of interrupt as appear of SDIO_DAT1*/
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#define ENABLE_GPIO_1_INT_MODE 0x88
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/** Scratch reg 3 2 : Configure GPIO-1 INT*/
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#define SCRATCH_REG_32 0xEE
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/** Card Control Registers : Card revision register */
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#define CARD_REVISION_REG 0xC8
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/** Firmware status 0 register (SCRATCH0_0) */
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#define CARD_FW_STATUS0_REG 0xe8
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/** Firmware status 1 register (SCRATCH0_1) */
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#define CARD_FW_STATUS1_REG 0xe9
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/** Rx length register (SCRATCH0_2) */
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#define CARD_RX_LEN_REG 0xea
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/** Rx unit register (SCRATCH0_3) */
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#define CARD_RX_UNIT_REG 0xeb
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/** Card Control Registers : Card OCR 0 register */
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#define CARD_OCR_0_REG 0xD4
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/** Card Control Registers : Card OCR 1 register */
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#define CARD_OCR_1_REG 0xD5
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/** Card Control Registers : Card OCR 3 register */
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#define CARD_OCR_3_REG 0xD6
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/** Card Control Registers : Card config register */
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#define CARD_CONFIG_REG 0xD7
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/** Card Control Registers : Miscellaneous Configuration Register */
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#define CARD_MISC_CFG_REG 0xD8
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/** Card Control Registers : sdio new mode register 1 */
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#define CARD_CONFIG_2_1_REG 0xD9
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/** Card Control Registers : cmd53 new mode */
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#define CMD53_NEW_MODE (0x1U << 0)
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/** Card Control Registers : cmd53 tx len format 1 (0x10) */
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#define CMD53_TX_LEN_FORMAT_1 (0x1U << 4)
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/** Card Control Registers : cmd53 tx len format 2 (0x20)*/
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#define CMD53_TX_LEN_FORMAT_2 (0x1U << 5)
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/** Card Control Registers : cmd53 rx len format 1 (0x40) */
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#define CMD53_RX_LEN_FORMAT_1 (0x1U << 6)
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/** Card Control Registers : cmd53 rx len format 2 (0x80)*/
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#define CMD53_RX_LEN_FORMAT_2 (0x1U << 7)
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/** Card Control Registers : sdio new mode register 2 */
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#define CARD_CONFIG_2_2_REG 0xDA
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/** Card Control Registers : test data out (0x01) */
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#define TEST_DATA_OUT_1 (0x1U << 0)
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/** Card Control Registers : test data out (0x02) */
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#define TEST_DATA_OUT_2 (0x1U << 1)
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/** Card Control Registers : test data out (0x04) */
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#define TEST_DATA_OUT_3 (0x1U << 2)
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/** Card Control Registers : test data out (0x08) */
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#define TEST_DATA_OUT_4 (0x1U << 3)
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/** Card Control Registers : test cmd out (0x10) */
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#define TEST_CMD_OUT (0x1U << 4)
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/** Card Control Registers : sdio new mode register 3 */
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#define CARD_CONFIG_2_3_REG 0xDB
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/** Card Control Registers : test data enable (0x01) */
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#define TEST_DATA_EN_1 (0x1U << 0)
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/** Card Control Registers : test data enable (0x02) */
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#define TEST_DATA_EN_2 (0x1U << 1)
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/** Card Control Registers : test data enable (0x04) */
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#define TEST_DATA_EN_3 (0x1U << 2)
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/** Card Control Registers : test data enable (0x08) */
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#define TEST_DATA_EN_4 (0x1U << 3)
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/** Card Control Registers : test cmd enable (0x10) */
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#define TEST_CMD_EN (0x1U << 4)
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/** Card Control Registers : test mode (0x20) */
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#define TEST_MODE (0x1U << 5)
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/** Card Control Registers : Debug 0 register */
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#define DEBUG_0_REG 0xDC
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/** Card Control Registers : SD test BUS 0 */
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#define SD_TESTBUS0 (0x1U)
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/** Card Control Registers : Debug 1 register */
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#define DEBUG_1_REG 0xDD
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/** Card Control Registers : SD test BUS 1 */
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#define SD_TESTBUS1 (0x1U)
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/** Card Control Registers : Debug 2 register */
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#define DEBUG_2_REG 0xDE
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/** Card Control Registers : SD test BUS 2 */
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#define SD_TESTBUS2 (0x1U)
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/** Card Control Registers : Debug 3 register */
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#define DEBUG_3_REG 0xDF
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/** Card Control Registers : SD test BUS 3 */
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#define SD_TESTBUS3 (0x1U)
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/** Host Control Registers : I/O port 0 */
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#define IO_PORT_0_REG 0xE4
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/** Host Control Registers : I/O port 1 */
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#define IO_PORT_1_REG 0xE5
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/** Host Control Registers : I/O port 2 */
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#define IO_PORT_2_REG 0xE6
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#define FW_RESET_REG 0x0EE
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#define FW_RESET_VAL 0x99
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/** Event header Len*/
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#define MLAN_EVENT_HEADER_LEN 8
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/** SDIO byte mode size */
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#define MAX_BYTE_MODE_SIZE 512
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#if defined(SDIO_MULTI_PORT_TX_AGGR) || defined(SDIO_MULTI_PORT_RX_AGGR)
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/** The base address for packet with multiple ports aggregation */
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#define SDIO_MPA_ADDR_BASE 0x1000
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#endif
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#ifdef SDIO_MULTI_PORT_TX_AGGR
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/** SDIO Tx aggregation in progress ? */
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#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
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/** SDIO Tx aggregation buffer room for next packet ? */
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#define MP_TX_AGGR_BUF_HAS_ROOM(a, mbuf, len) \
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(((a->mpa_tx.buf_len) + len) <= (a->mpa_tx.buf_size))
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/** Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
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#define MP_TX_AGGR_BUF_PUT(a, mbuf, port) do { \
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pmadapter->callbacks.moal_memmove(a->pmoal_handle, \
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&a->mpa_tx.buf[a->mpa_tx.buf_len], \
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mbuf->pbuf+mbuf->data_offset, mbuf->data_len);\
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a->mpa_tx.buf_len += mbuf->data_len; \
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a->mpa_tx.mp_wr_info[a->mpa_tx.pkt_cnt] = \
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*(t_u16 *)(mbuf->pbuf+mbuf->data_offset); \
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if (!a->mpa_tx.pkt_cnt) { \
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a->mpa_tx.start_port = port; \
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} \
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a->mpa_tx.ports |= (1 << port); \
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a->mpa_tx.pkt_cnt++; \
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} while (0)
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#define MP_TX_AGGR_BUF_PUT_SG(a, mbuf, port) do { \
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a->mpa_tx.buf_len += mbuf->data_len; \
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a->mpa_tx.mp_wr_info[a->mpa_tx.pkt_cnt] = \
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*(t_u16 *)(mbuf->pbuf+mbuf->data_offset); \
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a->mpa_tx.mbuf_arr[a->mpa_tx.pkt_cnt] = mbuf; \
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if (!a->mpa_tx.pkt_cnt) { \
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a->mpa_tx.start_port = port; \
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} \
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a->mpa_tx.ports |= (1 << port); \
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a->mpa_tx.pkt_cnt++; \
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} while (0)
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/** SDIO Tx aggregation limit ? */
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#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) ((a->mpa_tx.pkt_cnt) \
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== (a->mpa_tx.pkt_aggr_limit))
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/** SDIO Tx aggregation port limit ? */
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#define MP_TX_AGGR_PORT_LIMIT_REACHED(a) (MFALSE)
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/** Reset SDIO Tx aggregation buffer parameters */
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#define MP_TX_AGGR_BUF_RESET(a) do { \
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memset(a, a->mpa_tx.mp_wr_info, 0, sizeof(a->mpa_tx.mp_wr_info)); \
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a->mpa_tx.pkt_cnt = 0; \
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a->mpa_tx.buf_len = 0; \
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a->mpa_tx.ports = 0; \
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a->mpa_tx.start_port = 0; \
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} while (0)
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#endif /* SDIO_MULTI_PORT_TX_AGGR */
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#ifdef SDIO_MULTI_PORT_RX_AGGR
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/** SDIO Rx aggregation limit ? */
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#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) (a->mpa_rx.pkt_cnt \
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== a->mpa_rx.pkt_aggr_limit)
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/** SDIO Rx aggregation port limit ? */
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/** this is for test only, because port 0 is reserved for control port */
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/* #define MP_RX_AGGR_PORT_LIMIT_REACHED(a) (a->curr_rd_port == 1) */
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/* receive packets aggregated up to a half of mp_end_port */
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/* note: hw rx wraps round only after port (MAX_PORT-1) */
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#define MP_RX_AGGR_PORT_LIMIT_REACHED(a) \
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(((a->curr_rd_port < a->mpa_rx.start_port) && \
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(((MAX_PORT - a->mpa_rx.start_port) + a->curr_rd_port) \
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>= (a->mp_end_port >> 1))) || \
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((a->curr_rd_port - a->mpa_rx.start_port) >= \
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(a->mp_end_port >> 1)))
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/** SDIO Rx aggregation in progress ? */
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#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
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/** SDIO Rx aggregation buffer room for next packet ? */
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#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
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((a->mpa_rx.buf_len + rx_len) <= a->mpa_rx.buf_size)
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/** Prepare to copy current packet from card to SDIO Rx aggregation buffer */
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#define MP_RX_AGGR_SETUP(a, mbuf, port, rx_len) do { \
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a->mpa_rx.buf_len += rx_len; \
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if (!a->mpa_rx.pkt_cnt) { \
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a->mpa_rx.start_port = port; \
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} \
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a->mpa_rx.ports |= (1 << port); \
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a->mpa_rx.mbuf_arr[a->mpa_rx.pkt_cnt] = mbuf; \
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a->mpa_rx.len_arr[a->mpa_rx.pkt_cnt] = rx_len; \
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a->mpa_rx.pkt_cnt++; \
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} while (0)
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/** Reset SDIO Rx aggregation buffer parameters */
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#define MP_RX_AGGR_BUF_RESET(a) do { \
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a->mpa_rx.pkt_cnt = 0; \
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a->mpa_rx.buf_len = 0; \
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a->mpa_rx.ports = 0; \
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a->mpa_rx.start_port = 0; \
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} while (0)
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#endif /* SDIO_MULTI_PORT_RX_AGGR */
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/** Enable host interrupt */
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mlan_status wlan_enable_host_int(pmlan_adapter pmadapter);
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/** Probe and initialization function */
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mlan_status wlan_sdio_probe(pmlan_adapter pmadapter);
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/** multi interface download check */
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mlan_status wlan_check_winner_status(mlan_adapter *pmadapter, t_u32 *val);
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#ifdef SDIO_MULTI_PORT_TX_AGGR
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mlan_status wlan_send_mp_aggr_buf(mlan_adapter *pmadapter);
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#endif
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#if defined(SDIO_MULTI_PORT_RX_AGGR)
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mlan_status wlan_re_alloc_sdio_rx_mpa_buffer(IN mlan_adapter *pmadapter);
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#endif
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void wlan_decode_spa_buffer(mlan_adapter *pmadapter, t_u8 *buf, t_u32 len);
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t_void wlan_sdio_deaggr_rx_pkt(IN pmlan_adapter pmadapter, mlan_buffer *pmbuf);
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/** Firmware status check */
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mlan_status wlan_check_fw_status(mlan_adapter *pmadapter, t_u32 pollnum);
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/** Read interrupt status */
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mlan_status wlan_interrupt(pmlan_adapter pmadapter);
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/** Process Interrupt Status */
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mlan_status wlan_process_int_status(mlan_adapter *pmadapter);
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/** Transfer data to card */
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mlan_status wlan_sdio_host_to_card(mlan_adapter *pmadapter, t_u8 type,
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mlan_buffer *mbuf, mlan_tx_param *tx_param);
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mlan_status wlan_set_sdio_gpio_int(IN pmlan_private priv);
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mlan_status wlan_cmd_sdio_gpio_int(pmlan_private pmpriv,
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IN HostCmd_DS_COMMAND *cmd,
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IN t_u16 cmd_action, IN t_void *pdata_buf);
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mlan_status wlan_reset_fw(pmlan_adapter pmadapter);
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#endif /* _MLAN_SDIO_H */
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