/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ARM_CP15_H
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#define __ASM_ARM_CP15_H
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#include <asm/barrier.h>
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/*
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* CR1 bits (CP#15 CR1)
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_W (1 << 3) /* Write buffer enable */
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#define CR_P (1 << 4) /* 32-bit exception handler */
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#define CR_D (1 << 5) /* 32-bit data address range */
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#define CR_L (1 << 6) /* Implementation defined */
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#define CR_B (1 << 7) /* Big endian */
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#define CR_S (1 << 8) /* System MMU protection */
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#define CR_R (1 << 9) /* ROM MMU protection */
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#define CR_F (1 << 10) /* Implementation defined */
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#define CR_Z (1 << 11) /* Implementation defined */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#define CR_RR (1 << 14) /* Round Robin cache replacement */
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#define CR_L4 (1 << 15) /* LDR pc can set T bit */
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#define CR_DT (1 << 16)
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#ifdef CONFIG_MMU
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#define CR_HA (1 << 17) /* Hardware management of Access Flag */
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#else
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#define CR_BR (1 << 17) /* MPU Background region enable (PMSA) */
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#endif
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#define CR_IT (1 << 18)
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#define CR_ST (1 << 19)
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#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
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#define CR_U (1 << 22) /* Unaligned access operation */
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#define CR_XP (1 << 23) /* Extended page tables */
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#define CR_VE (1 << 24) /* Vectored interrupts */
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#define CR_EE (1 << 25) /* Exception (Big) Endian */
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#define CR_TRE (1 << 28) /* TEX remap enable */
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#define CR_AFE (1 << 29) /* Access flag enable */
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#define CR_TE (1 << 30) /* Thumb exception enable */
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#ifndef __ASSEMBLY__
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#if __LINUX_ARM_ARCH__ >= 4
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#define vectors_high() (get_cr() & CR_V)
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#else
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#define vectors_high() (0)
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#endif
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#ifdef CONFIG_CPU_CP15
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#include <asm/vdso/cp15.h>
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extern unsigned long cr_alignment; /* defined in entry-armv.S */
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static inline unsigned long get_cr(void)
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{
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unsigned long val;
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asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_cr(unsigned long val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
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: : "r" (val) : "cc");
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isb();
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}
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static inline unsigned int get_auxcr(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val));
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return val;
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}
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static inline void set_auxcr(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
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: : "r" (val));
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isb();
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}
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#define CPACC_FULL(n) (3 << (n * 2))
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#define CPACC_SVC(n) (1 << (n * 2))
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#define CPACC_DISABLE(n) (0 << (n * 2))
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static inline unsigned int get_copro_access(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
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: "=r" (val) : : "cc");
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return val;
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}
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static inline void set_copro_access(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
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: : "r" (val) : "cc");
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isb();
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}
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#else /* ifdef CONFIG_CPU_CP15 */
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/*
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* cr_alignment is tightly coupled to cp15 (at least in the minds of the
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* developers). Yielding 0 for machines without a cp15 (and making it
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* read-only) is fine for most cases and saves quite some #ifdeffery.
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*/
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#define cr_alignment UL(0)
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static inline unsigned long get_cr(void)
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{
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return 0;
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}
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#endif /* ifdef CONFIG_CPU_CP15 / else */
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#endif /* ifndef __ASSEMBLY__ */
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#endif
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