/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#ifndef __ASSEMBLY__
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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#if __LINUX_ARM_ARCH__ >= 7 || \
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(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
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#define sev() __asm__ __volatile__ ("sev" : : : "memory")
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#define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
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#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
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#else
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#define wfe() do { } while (0)
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#endif
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#if __LINUX_ARM_ARCH__ >= 7
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#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")
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#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")
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#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")
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#ifdef CONFIG_THUMB2_KERNEL
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#define CSDB ".inst.w 0xf3af8014"
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#else
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#define CSDB ".inst 0xe320f014"
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#endif
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#define csdb() __asm__ __volatile__(CSDB : : : "memory")
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#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
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#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
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: : "r" (0) : "memory")
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#elif defined(CONFIG_CPU_FA526)
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#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
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#else
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#define isb(x) __asm__ __volatile__ ("" : : : "memory")
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#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
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#endif
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#ifndef CSDB
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#define CSDB
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#endif
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#ifndef csdb
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#define csdb()
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#endif
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#ifdef CONFIG_ARM_HEAVY_MB
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extern void (*soc_mb)(void);
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extern void arm_heavy_mb(void);
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#define __arm_heavy_mb(x...) do { dsb(x); arm_heavy_mb(); } while (0)
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#else
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#define __arm_heavy_mb(x...) dsb(x)
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#endif
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#if defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
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#define mb() __arm_heavy_mb()
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#define rmb() dsb()
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#define wmb() __arm_heavy_mb(st)
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#define dma_rmb() dmb(osh)
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#define dma_wmb() dmb(oshst)
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#else
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define dma_rmb() barrier()
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#define dma_wmb() barrier()
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#endif
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#define __smp_mb() dmb(ish)
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#define __smp_rmb() __smp_mb()
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#define __smp_wmb() dmb(ishst)
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#ifdef CONFIG_CPU_SPECTRE
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static inline unsigned long array_index_mask_nospec(unsigned long idx,
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unsigned long sz)
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{
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unsigned long mask;
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asm volatile(
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"cmp %1, %2\n"
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" sbc %0, %1, %1\n"
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CSDB
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: "=r" (mask)
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: "r" (idx), "Ir" (sz)
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: "cc");
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return mask;
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}
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#define array_index_mask_nospec array_index_mask_nospec
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#endif
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#include <asm-generic/barrier.h>
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_BARRIER_H */
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