/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __S390_ASM_SIGP_H
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#define __S390_ASM_SIGP_H
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/* SIGP order codes */
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#define SIGP_SENSE 1
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#define SIGP_EXTERNAL_CALL 2
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#define SIGP_EMERGENCY_SIGNAL 3
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#define SIGP_START 4
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#define SIGP_STOP 5
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#define SIGP_RESTART 6
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#define SIGP_STOP_AND_STORE_STATUS 9
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#define SIGP_INITIAL_CPU_RESET 11
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#define SIGP_CPU_RESET 12
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#define SIGP_SET_PREFIX 13
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#define SIGP_STORE_STATUS_AT_ADDRESS 14
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#define SIGP_SET_ARCHITECTURE 18
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#define SIGP_COND_EMERGENCY_SIGNAL 19
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#define SIGP_SENSE_RUNNING 21
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#define SIGP_SET_MULTI_THREADING 22
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#define SIGP_STORE_ADDITIONAL_STATUS 23
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/* SIGP condition codes */
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#define SIGP_CC_ORDER_CODE_ACCEPTED 0
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#define SIGP_CC_STATUS_STORED 1
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#define SIGP_CC_BUSY 2
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#define SIGP_CC_NOT_OPERATIONAL 3
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/* SIGP cpu status bits */
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#define SIGP_STATUS_INVALID_ORDER 0x00000002UL
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#define SIGP_STATUS_CHECK_STOP 0x00000010UL
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#define SIGP_STATUS_STOPPED 0x00000040UL
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#define SIGP_STATUS_EXT_CALL_PENDING 0x00000080UL
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#define SIGP_STATUS_INVALID_PARAMETER 0x00000100UL
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#define SIGP_STATUS_INCORRECT_STATE 0x00000200UL
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#define SIGP_STATUS_NOT_RUNNING 0x00000400UL
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#ifndef __ASSEMBLY__
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static inline int ____pcpu_sigp(u16 addr, u8 order, unsigned long parm,
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u32 *status)
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{
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register unsigned long reg1 asm ("1") = parm;
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int cc;
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asm volatile(
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" sigp %1,%2,0(%3)\n"
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" ipm %0\n"
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" srl %0,28\n"
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: "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc");
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*status = reg1;
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return cc;
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}
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static inline int __pcpu_sigp(u16 addr, u8 order, unsigned long parm,
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u32 *status)
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{
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u32 _status;
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int cc;
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cc = ____pcpu_sigp(addr, order, parm, &_status);
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if (status && cc == SIGP_CC_STATUS_STORED)
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*status = _status;
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return cc;
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __S390_ASM_SIGP_H */
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