/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Performance counter support for POWER9 processors.
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*
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* Copyright 2016 Madhavan Srinivasan, IBM Corporation.
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*/
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/*
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* Power9 event codes.
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*/
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EVENT(PM_CYC, 0x0001e)
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EVENT(PM_ICT_NOSLOT_CYC, 0x100f8)
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EVENT(PM_CMPLU_STALL, 0x1e054)
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EVENT(PM_INST_CMPL, 0x00002)
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EVENT(PM_BR_CMPL, 0x4d05e)
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EVENT(PM_BR_MPRED_CMPL, 0x400f6)
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/* All L1 D cache load references counted at finish, gated by reject */
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EVENT(PM_LD_REF_L1, 0x100fc)
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/* Load Missed L1 */
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EVENT(PM_LD_MISS_L1_FIN, 0x2c04e)
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EVENT(PM_LD_MISS_L1, 0x3e054)
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/* Alternate event code for PM_LD_MISS_L1 */
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EVENT(PM_LD_MISS_L1_ALT, 0x400f0)
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/* Store Missed L1 */
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EVENT(PM_ST_MISS_L1, 0x300f0)
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/* L1 cache data prefetches */
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EVENT(PM_L1_PREF, 0x20054)
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/* Instruction fetches from L1 */
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EVENT(PM_INST_FROM_L1, 0x04080)
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/* Demand iCache Miss */
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EVENT(PM_L1_ICACHE_MISS, 0x200fd)
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/* Instruction Demand sectors wriittent into IL1 */
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EVENT(PM_L1_DEMAND_WRITE, 0x0408c)
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/* Instruction prefetch written into IL1 */
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EVENT(PM_IC_PREF_WRITE, 0x0488c)
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/* The data cache was reloaded from local core's L3 due to a demand load */
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EVENT(PM_DATA_FROM_L3, 0x4c042)
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/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
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EVENT(PM_DATA_FROM_L3MISS, 0x300fe)
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/* All successful D-side store dispatches for this thread */
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EVENT(PM_L2_ST, 0x16880)
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/* All successful D-side store dispatches for this thread that were L2 Miss */
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EVENT(PM_L2_ST_MISS, 0x26880)
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/* Total HW L3 prefetches(Load+store) */
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EVENT(PM_L3_PREF_ALL, 0x4e052)
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/* Data PTEG reload */
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EVENT(PM_DTLB_MISS, 0x300fc)
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/* ITLB Reloaded */
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EVENT(PM_ITLB_MISS, 0x400fc)
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/* Run_Instructions */
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EVENT(PM_RUN_INST_CMPL, 0x500fa)
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/* Alternate event code for PM_RUN_INST_CMPL */
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EVENT(PM_RUN_INST_CMPL_ALT, 0x400fa)
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/* Run_cycles */
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EVENT(PM_RUN_CYC, 0x600f4)
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/* Alternate event code for Run_cycles */
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EVENT(PM_RUN_CYC_ALT, 0x200f4)
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/* Instruction Dispatched */
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EVENT(PM_INST_DISP, 0x200f2)
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EVENT(PM_INST_DISP_ALT, 0x300f2)
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/* Branch event that are not strongly biased */
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EVENT(PM_BR_2PATH, 0x20036)
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/* ALternate branch event that are not strongly biased */
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EVENT(PM_BR_2PATH_ALT, 0x40036)
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/* Blacklisted events */
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EVENT(PM_MRK_ST_DONE_L2, 0x10134)
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EVENT(PM_RADIX_PWC_L1_HIT, 0x1f056)
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EVENT(PM_FLOP_CMPL, 0x100f4)
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EVENT(PM_MRK_NTF_FIN, 0x20112)
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EVENT(PM_RADIX_PWC_L2_HIT, 0x2d024)
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EVENT(PM_IFETCH_THROTTLE, 0x3405e)
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EVENT(PM_MRK_L2_TM_ST_ABORT_SISTER, 0x3e15c)
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EVENT(PM_RADIX_PWC_L3_HIT, 0x3f056)
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EVENT(PM_RUN_CYC_SMT2_MODE, 0x3006c)
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EVENT(PM_TM_TX_PASS_RUN_INST, 0x4e014)
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EVENT(PM_DISP_HELD_SYNC_HOLD, 0x4003c)
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EVENT(PM_DTLB_MISS_16G, 0x1c058)
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EVENT(PM_DERAT_MISS_2M, 0x1c05a)
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EVENT(PM_DTLB_MISS_2M, 0x1c05c)
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EVENT(PM_MRK_DTLB_MISS_1G, 0x1d15c)
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EVENT(PM_DTLB_MISS_4K, 0x2c056)
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EVENT(PM_DERAT_MISS_1G, 0x2c05a)
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EVENT(PM_MRK_DERAT_MISS_2M, 0x2d152)
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EVENT(PM_MRK_DTLB_MISS_4K, 0x2d156)
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EVENT(PM_MRK_DTLB_MISS_16G, 0x2d15e)
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EVENT(PM_DTLB_MISS_64K, 0x3c056)
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EVENT(PM_MRK_DERAT_MISS_1G, 0x3d152)
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EVENT(PM_MRK_DTLB_MISS_64K, 0x3d156)
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EVENT(PM_DTLB_MISS_16M, 0x4c056)
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EVENT(PM_DTLB_MISS_1G, 0x4c05a)
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EVENT(PM_MRK_DTLB_MISS_16M, 0x4c15e)
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/*
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* Memory Access Events
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*
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* Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)
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* To enable capturing of memory profiling, these MMCRA bits
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* needs to be programmed and corresponding raw event format
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* encoding.
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*
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* MMCRA bits encoding needed are
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* SM (Sampling Mode)
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* EM (Eligibility for Random Sampling)
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* TECE (Threshold Event Counter Event)
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* TS (Threshold Start Event)
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* TE (Threshold End Event)
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*
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* Corresponding Raw Encoding bits:
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* sample [EM,SM]
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* thresh_sel (TECE)
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* thresh start (TS)
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* thresh end (TE)
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*/
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EVENT(MEM_LOADS, 0x34340401e0)
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EVENT(MEM_STORES, 0x343c0401e0)
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