/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016 - ARM Ltd
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*
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* stage2 page table helpers
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*/
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#ifndef __ARM64_S2_PGTABLE_H_
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#define __ARM64_S2_PGTABLE_H_
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#include <linux/pgtable.h>
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/*
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* PGDIR_SHIFT determines the size a top-level page table entry can map
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* and depends on the number of levels in the page table. Compute the
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* PGDIR_SHIFT for a given number of levels.
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*/
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#define pt_levels_pgdir_shift(lvls) ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - (lvls))
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/*
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* The hardware supports concatenation of up to 16 tables at stage2 entry
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* level and we use the feature whenever possible, which means we resolve 4
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* additional bits of address at the entry level.
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*
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* This implies, the total number of page table levels required for
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* IPA_SHIFT at stage2 expected by the hardware can be calculated using
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* the same logic used for the (non-collapsable) stage1 page tables but for
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* (IPA_SHIFT - 4).
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*/
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#define stage2_pgtable_levels(ipa) ARM64_HW_PGTABLE_LEVELS((ipa) - 4)
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#define kvm_stage2_levels(kvm) VTCR_EL2_LVLS(kvm->arch.vtcr)
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/* stage2_pgdir_shift() is the size mapped by top-level stage2 entry for the VM */
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#define stage2_pgdir_shift(kvm) pt_levels_pgdir_shift(kvm_stage2_levels(kvm))
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#define stage2_pgdir_size(kvm) (1ULL << stage2_pgdir_shift(kvm))
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#define stage2_pgdir_mask(kvm) ~(stage2_pgdir_size(kvm) - 1)
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/*
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* kvm_mmmu_cache_min_pages() is the number of pages required to install
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* a stage-2 translation. We pre-allocate the entry level page table at
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* the VM creation.
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*/
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#define kvm_mmu_cache_min_pages(kvm) (kvm_stage2_levels(kvm) - 1)
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static inline phys_addr_t
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stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end)
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{
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phys_addr_t boundary = (addr + stage2_pgdir_size(kvm)) & stage2_pgdir_mask(kvm);
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return (boundary - 1 < end - 1) ? boundary : end;
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}
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#endif /* __ARM64_S2_PGTABLE_H_ */
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