/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_CPUTYPE_H
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#define __ASM_CPUTYPE_H
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#define INVALID_HWID ULONG_MAX
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#define MPIDR_UP_BITMASK (0x1 << 30)
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#define MPIDR_MT_BITMASK (0x1 << 24)
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#define MPIDR_HWID_BITMASK UL(0xff00ffffff)
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#define MPIDR_LEVEL_BITS_SHIFT 3
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#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
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#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
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#define MPIDR_LEVEL_SHIFT(level) \
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(((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
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#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
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((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
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#define MIDR_REVISION_MASK 0xf
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#define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
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#define MIDR_PARTNUM_SHIFT 4
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#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
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#define MIDR_PARTNUM(midr) \
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(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
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#define MIDR_ARCHITECTURE_SHIFT 16
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#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
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#define MIDR_ARCHITECTURE(midr) \
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(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
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#define MIDR_VARIANT_SHIFT 20
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#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
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#define MIDR_VARIANT(midr) \
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(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
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#define MIDR_IMPLEMENTOR_SHIFT 24
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#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
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#define MIDR_IMPLEMENTOR(midr) \
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(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
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#define MIDR_CPU_MODEL(imp, partnum) \
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((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \
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(0xf << MIDR_ARCHITECTURE_SHIFT) | \
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((partnum) << MIDR_PARTNUM_SHIFT))
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#define MIDR_CPU_VAR_REV(var, rev) \
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(((var) << MIDR_VARIANT_SHIFT) | (rev))
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#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
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MIDR_ARCHITECTURE_MASK)
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#define ARM_CPU_IMP_ARM 0x41
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#define ARM_CPU_IMP_APM 0x50
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#define ARM_CPU_IMP_CAVIUM 0x43
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#define ARM_CPU_IMP_BRCM 0x42
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#define ARM_CPU_IMP_QCOM 0x51
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#define ARM_CPU_IMP_NVIDIA 0x4E
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#define ARM_CPU_IMP_FUJITSU 0x46
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#define ARM_CPU_IMP_HISI 0x48
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#define ARM_CPU_IMP_APPLE 0x61
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#define ARM_CPU_IMP_AMPERE 0xC0
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#define ARM_CPU_PART_AEM_V8 0xD0F
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#define ARM_CPU_PART_FOUNDATION 0xD00
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#define ARM_CPU_PART_CORTEX_A57 0xD07
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#define ARM_CPU_PART_CORTEX_A72 0xD08
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#define ARM_CPU_PART_CORTEX_A53 0xD03
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#define ARM_CPU_PART_CORTEX_A73 0xD09
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#define ARM_CPU_PART_CORTEX_A75 0xD0A
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#define ARM_CPU_PART_CORTEX_A35 0xD04
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#define ARM_CPU_PART_CORTEX_A55 0xD05
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#define ARM_CPU_PART_CORTEX_A76 0xD0B
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#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
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#define ARM_CPU_PART_CORTEX_A77 0xD0D
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#define ARM_CPU_PART_NEOVERSE_V1 0xD40
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#define ARM_CPU_PART_CORTEX_A78 0xD41
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#define ARM_CPU_PART_CORTEX_A78AE 0xD42
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#define ARM_CPU_PART_CORTEX_X1 0xD44
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#define ARM_CPU_PART_CORTEX_A510 0xD46
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#define ARM_CPU_PART_CORTEX_A710 0xD47
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#define ARM_CPU_PART_CORTEX_X2 0xD48
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#define ARM_CPU_PART_NEOVERSE_N2 0xD49
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#define ARM_CPU_PART_CORTEX_A78C 0xD4B
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#define APM_CPU_PART_POTENZA 0x000
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#define CAVIUM_CPU_PART_THUNDERX 0x0A1
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#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
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#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
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#define CAVIUM_CPU_PART_THUNDERX2 0x0AF
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#define BRCM_CPU_PART_BRAHMA_B53 0x100
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#define BRCM_CPU_PART_VULCAN 0x516
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#define QCOM_CPU_PART_FALKOR_V1 0x800
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#define QCOM_CPU_PART_FALKOR 0xC00
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#define QCOM_CPU_PART_KRYO 0x200
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#define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800
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#define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801
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#define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803
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#define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804
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#define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805
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#define NVIDIA_CPU_PART_DENVER 0x003
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#define NVIDIA_CPU_PART_CARMEL 0x004
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#define FUJITSU_CPU_PART_A64FX 0x001
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#define HISI_CPU_PART_TSV110 0xD01
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#define APPLE_CPU_PART_M1_ICESTORM 0x022
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#define APPLE_CPU_PART_M1_FIRESTORM 0x023
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#define AMPERE_CPU_PART_AMPERE1 0xAC3
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#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
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#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
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#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
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#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
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#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
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#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
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#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
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#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
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#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
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#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
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#define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
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#define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
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#define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
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#define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
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#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
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#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
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#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
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#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
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#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
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#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
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#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
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#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
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#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
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#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
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#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
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#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
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#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
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#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
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#define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)
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#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
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#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
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#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
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#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
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#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
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#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
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#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
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#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
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#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
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#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
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#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
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/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
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#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
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#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
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#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
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#ifndef __ASSEMBLY__
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#include <asm/sysreg.h>
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#define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
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/*
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* Represent a range of MIDR values for a given CPU model and a
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* range of variant/revision values.
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*
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* @model - CPU model as defined by MIDR_CPU_MODEL
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* @rv_min - Minimum value for the revision/variant as defined by
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* MIDR_CPU_VAR_REV
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* @rv_max - Maximum value for the variant/revision for the range.
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*/
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struct midr_range {
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u32 model;
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u32 rv_min;
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u32 rv_max;
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};
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#define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \
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{ \
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.model = m, \
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.rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \
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.rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \
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}
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#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
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#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
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#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
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static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
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u32 rv_max)
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{
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u32 _model = midr & MIDR_CPU_MODEL_MASK;
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u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);
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return _model == model && rv >= rv_min && rv <= rv_max;
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}
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static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
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{
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return midr_is_cpu_model_range(midr, range->model,
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range->rv_min, range->rv_max);
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}
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static inline bool
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is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
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{
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while (ranges->model)
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if (is_midr_in_range(midr, ranges++))
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return true;
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return false;
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}
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/*
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* The CPU ID never changes at run time, so we might as well tell the
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* compiler that it's constant. Use this function to read the CPU ID
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* rather than directly reading processor_id or read_cpuid() directly.
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*/
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static inline u32 __attribute_const__ read_cpuid_id(void)
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{
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return read_cpuid(MIDR_EL1);
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}
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static inline u64 __attribute_const__ read_cpuid_mpidr(void)
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{
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return read_cpuid(MPIDR_EL1);
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}
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static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
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{
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return MIDR_IMPLEMENTOR(read_cpuid_id());
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}
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static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
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{
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return MIDR_PARTNUM(read_cpuid_id());
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}
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static inline u32 __attribute_const__ read_cpuid_cachetype(void)
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{
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return read_cpuid(CTR_EL0);
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}
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#endif /* __ASSEMBLY__ */
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#endif
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