/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* ARM DynamIQ Shared Unit (DSU) PMU Low level register access routines.
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*
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* Copyright (C) ARM Limited, 2017.
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*
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* Author: Suzuki K Poulose <suzuki.poulose@arm.com>
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*/
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#include <linux/bitops.h>
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#include <linux/build_bug.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/barrier.h>
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#include <asm/sysreg.h>
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#define CLUSTERPMCR_EL1 sys_reg(3, 0, 15, 5, 0)
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#define CLUSTERPMCNTENSET_EL1 sys_reg(3, 0, 15, 5, 1)
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#define CLUSTERPMCNTENCLR_EL1 sys_reg(3, 0, 15, 5, 2)
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#define CLUSTERPMOVSSET_EL1 sys_reg(3, 0, 15, 5, 3)
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#define CLUSTERPMOVSCLR_EL1 sys_reg(3, 0, 15, 5, 4)
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#define CLUSTERPMSELR_EL1 sys_reg(3, 0, 15, 5, 5)
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#define CLUSTERPMINTENSET_EL1 sys_reg(3, 0, 15, 5, 6)
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#define CLUSTERPMINTENCLR_EL1 sys_reg(3, 0, 15, 5, 7)
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#define CLUSTERPMCCNTR_EL1 sys_reg(3, 0, 15, 6, 0)
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#define CLUSTERPMXEVTYPER_EL1 sys_reg(3, 0, 15, 6, 1)
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#define CLUSTERPMXEVCNTR_EL1 sys_reg(3, 0, 15, 6, 2)
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#define CLUSTERPMMDCR_EL1 sys_reg(3, 0, 15, 6, 3)
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#define CLUSTERPMCEID0_EL1 sys_reg(3, 0, 15, 6, 4)
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#define CLUSTERPMCEID1_EL1 sys_reg(3, 0, 15, 6, 5)
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static inline u32 __dsu_pmu_read_pmcr(void)
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{
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return read_sysreg_s(CLUSTERPMCR_EL1);
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}
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static inline void __dsu_pmu_write_pmcr(u32 val)
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{
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write_sysreg_s(val, CLUSTERPMCR_EL1);
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isb();
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}
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static inline u32 __dsu_pmu_get_reset_overflow(void)
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{
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u32 val = read_sysreg_s(CLUSTERPMOVSCLR_EL1);
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/* Clear the bit */
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write_sysreg_s(val, CLUSTERPMOVSCLR_EL1);
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isb();
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return val;
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}
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static inline void __dsu_pmu_select_counter(int counter)
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{
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write_sysreg_s(counter, CLUSTERPMSELR_EL1);
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isb();
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}
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static inline u64 __dsu_pmu_read_counter(int counter)
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{
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__dsu_pmu_select_counter(counter);
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return read_sysreg_s(CLUSTERPMXEVCNTR_EL1);
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}
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static inline void __dsu_pmu_write_counter(int counter, u64 val)
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{
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__dsu_pmu_select_counter(counter);
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write_sysreg_s(val, CLUSTERPMXEVCNTR_EL1);
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isb();
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}
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static inline void __dsu_pmu_set_event(int counter, u32 event)
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{
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__dsu_pmu_select_counter(counter);
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write_sysreg_s(event, CLUSTERPMXEVTYPER_EL1);
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isb();
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}
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static inline u64 __dsu_pmu_read_pmccntr(void)
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{
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return read_sysreg_s(CLUSTERPMCCNTR_EL1);
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}
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static inline void __dsu_pmu_write_pmccntr(u64 val)
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{
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write_sysreg_s(val, CLUSTERPMCCNTR_EL1);
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isb();
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}
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static inline void __dsu_pmu_disable_counter(int counter)
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{
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write_sysreg_s(BIT(counter), CLUSTERPMCNTENCLR_EL1);
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isb();
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}
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static inline void __dsu_pmu_enable_counter(int counter)
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{
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write_sysreg_s(BIT(counter), CLUSTERPMCNTENSET_EL1);
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isb();
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}
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static inline void __dsu_pmu_counter_interrupt_enable(int counter)
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{
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write_sysreg_s(BIT(counter), CLUSTERPMINTENSET_EL1);
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isb();
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}
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static inline void __dsu_pmu_counter_interrupt_disable(int counter)
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{
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write_sysreg_s(BIT(counter), CLUSTERPMINTENCLR_EL1);
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isb();
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}
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static inline u32 __dsu_pmu_read_pmceid(int n)
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{
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switch (n) {
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case 0:
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return read_sysreg_s(CLUSTERPMCEID0_EL1);
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case 1:
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return read_sysreg_s(CLUSTERPMCEID1_EL1);
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default:
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BUILD_BUG();
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return 0;
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}
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}
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