/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <sbi_utils/serial/sifive-uart.h>
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/* clang-format off */
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#define UART_REG_TXFIFO 0
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#define UART_REG_RXFIFO 1
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#define UART_REG_TXCTRL 2
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#define UART_REG_RXCTRL 3
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#define UART_REG_IE 4
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#define UART_REG_IP 5
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#define UART_REG_DIV 6
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#define UART_TXFIFO_FULL 0x80000000
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#define UART_RXFIFO_EMPTY 0x80000000
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#define UART_RXFIFO_DATA 0x000000ff
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#define UART_TXCTRL_TXEN 0x1
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#define UART_RXCTRL_RXEN 0x1
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/* clang-format on */
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static volatile void *uart_base;
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static u32 uart_in_freq;
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static u32 uart_baudrate;
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/**
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* Find minimum divisor divides in_freq to max_target_hz;
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* Based on uart driver n SiFive FSBL.
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*
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* f_baud = f_in / (div + 1) => div = (f_in / f_baud) - 1
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* The nearest integer solution requires rounding up as to not exceed max_target_hz.
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* div = ceil(f_in / f_baud) - 1
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* = floor((f_in - 1 + f_baud) / f_baud) - 1
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* This should not overflow as long as (f_in - 1 + f_baud) does not exceed
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* 2^32 - 1, which is unlikely since we represent frequencies in kHz.
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*/
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static inline unsigned int uart_min_clk_divisor(uint64_t in_freq,
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uint64_t max_target_hz)
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{
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uint64_t quotient = (in_freq + max_target_hz - 1) / (max_target_hz);
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/* Avoid underflow */
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if (quotient == 0) {
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return 0;
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} else {
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return quotient - 1;
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}
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}
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static u32 get_reg(u32 num)
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{
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return readl(uart_base + (num * 0x4));
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}
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static void set_reg(u32 num, u32 val)
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{
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writel(val, uart_base + (num * 0x4));
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}
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void sifive_uart_putc(char ch)
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{
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while (get_reg(UART_REG_TXFIFO) & UART_TXFIFO_FULL)
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;
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set_reg(UART_REG_TXFIFO, ch);
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}
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int sifive_uart_getc(void)
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{
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u32 ret = get_reg(UART_REG_RXFIFO);
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if (!(ret & UART_RXFIFO_EMPTY))
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return ret & UART_RXFIFO_DATA;
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return -1;
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}
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int sifive_uart_init(unsigned long base, u32 in_freq, u32 baudrate)
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{
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uart_base = (volatile void *)base;
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uart_in_freq = in_freq;
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uart_baudrate = baudrate;
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/* Configure baudrate */
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if (in_freq)
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set_reg(UART_REG_DIV, uart_min_clk_divisor(in_freq, baudrate));
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/* Disable interrupts */
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set_reg(UART_REG_IE, 0);
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/* Enable TX */
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set_reg(UART_REG_TXCTRL, UART_TXCTRL_TXEN);
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/* Enable Rx */
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set_reg(UART_REG_RXCTRL, UART_RXCTRL_RXEN);
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return 0;
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}
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