/** @file
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This driver does SA PCI Express ACPI table initialization.
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Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PciExpressInit.h"
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#include <Library/ConfigBlockLib.h>
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extern SYSTEM_AGENT_NVS_AREA_PROTOCOL mSaNvsAreaProtocol;
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extern SA_CONFIG_HOB *mSaConfigHob;
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/**
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PCI Express Dxe Initialization.
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Run before PCI Bus Init, where assignment of Bus, Memory,
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and I/O Resources are assigned.
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@param[in] SaPolicy - SA DXE Policy protocol
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@retval EFI_SUCCESS - Pci Express successfully started and ready to be used
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**/
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EFI_STATUS
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PciExpressInit (
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IN SA_POLICY_PROTOCOL *SaPolicy
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)
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{
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EFI_STATUS Status;
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PCIE_DXE_CONFIG *PcieDxeConfig;
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MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
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Status = GetConfigBlock ((VOID *) SaPolicy, &gPcieDxeConfigGuid, (VOID *)&PcieDxeConfig);
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ASSERT_EFI_ERROR (Status);
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Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
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mSaNvsAreaProtocol.Area->PackageCstateLimit = (UINT8) Msr.Bits.Limit;
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mSaNvsAreaProtocol.Area->PwrDnBundlesGlobalEnable = 0;
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if (mSaConfigHob != NULL) {
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mSaNvsAreaProtocol.Area->Peg0PowerDownUnusedBundles = mSaConfigHob->PowerDownUnusedBundles[0];
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mSaNvsAreaProtocol.Area->Peg1PowerDownUnusedBundles = mSaConfigHob->PowerDownUnusedBundles[1];
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mSaNvsAreaProtocol.Area->Peg2PowerDownUnusedBundles = mSaConfigHob->PowerDownUnusedBundles[2];
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if (SA_PEG_MAX_FUN > 3) {
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mSaNvsAreaProtocol.Area->Peg3PowerDownUnusedBundles = mSaConfigHob->PowerDownUnusedBundles[3];
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}
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}
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///
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/// LTR/OBFF
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///
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mSaNvsAreaProtocol.Area->Peg0LtrEnable = PcieDxeConfig->PegPwrOpt[0].LtrEnable;
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mSaNvsAreaProtocol.Area->Peg0ObffEnable = PcieDxeConfig->PegPwrOpt[0].ObffEnable;
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mSaNvsAreaProtocol.Area->Peg1LtrEnable = PcieDxeConfig->PegPwrOpt[1].LtrEnable;
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mSaNvsAreaProtocol.Area->Peg1ObffEnable = PcieDxeConfig->PegPwrOpt[1].ObffEnable;
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mSaNvsAreaProtocol.Area->Peg2LtrEnable = PcieDxeConfig->PegPwrOpt[2].LtrEnable;
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mSaNvsAreaProtocol.Area->Peg2ObffEnable = PcieDxeConfig->PegPwrOpt[2].ObffEnable;
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mSaNvsAreaProtocol.Area->PegLtrMaxSnoopLatency = LTR_MAX_SNOOP_LATENCY_VALUE;
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mSaNvsAreaProtocol.Area->PegLtrMaxNoSnoopLatency = LTR_MAX_NON_SNOOP_LATENCY_VALUE;
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return EFI_SUCCESS;
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}
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/**
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Find the Offset to a given Capabilities ID
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CAPID list:
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0x01 = PCI Power Management Interface
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0x04 = Slot Identification
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0x05 = MSI Capability
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0x10 = PCI Express Capability
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@param[in] Segment - Pci Segment Number
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@param[in] Bus - Pci Bus Number
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@param[in] Device - Pci Device Number
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@param[in] Function - Pci Function Number
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@param[in] CapId - CAPID to search for
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@retval 0 - CAPID not found
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@retval Other - CAPID found, Offset of desired CAPID
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**/
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UINT32
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PcieFindCapId (
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IN UINT8 Segment,
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT8 CapId
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)
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{
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UINT64 DeviceBaseAddress;
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UINT8 CapHeader;
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///
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/// Always start at Offset 0x34
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///
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DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Function, 0);
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CapHeader = PciSegmentRead8 (DeviceBaseAddress + PCI_CAPBILITY_POINTER_OFFSET);
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if (CapHeader == 0xFF) {
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return 0;
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}
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while (CapHeader != 0) {
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///
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/// Bottom 2 bits of the pointers are reserved per PCI Local Bus Spec 2.2
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///
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CapHeader &= ~(BIT1 + BIT0);
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///
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/// Search for desired CapID
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///
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if (PciSegmentRead8 (DeviceBaseAddress + CapHeader) == CapId) {
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return CapHeader;
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}
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CapHeader = PciSegmentRead8 (DeviceBaseAddress + CapHeader + 1);
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}
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return 0;
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}
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/**
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Search and return the offset of desired Pci Express Capability ID
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CAPID list:
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0x0001 = Advanced Error Rreporting Capability
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0x0002 = Virtual Channel Capability
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0x0003 = Device Serial Number Capability
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0x0004 = Power Budgeting Capability
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@param[in] Segment - Pci Segment Number
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@param[in] Bus - Pci Bus Number
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@param[in] Device - Pci Device Number
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@param[in] Function - Pci Function Number
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@param[in] CapId - Extended CAPID to search for
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@retval 0 - CAPID not found
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@retval Other - CAPID found, Offset of desired CAPID
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**/
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UINT32
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PcieFindExtendedCapId (
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IN UINT8 Segment,
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT16 CapId
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)
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{
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UINT64 DeviceBaseAddress;
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UINT16 CapHeaderOffset;
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UINT16 CapHeaderId;
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///
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/// Start to search at Offset 0x100
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/// Get Capability Header
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///
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DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Function, 0);
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CapHeaderId = 0;
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CapHeaderOffset = 0x100;
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while (CapHeaderOffset != 0 && CapHeaderId != 0xFFFF) {
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///
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/// Search for desired CapID
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///
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CapHeaderId = PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset);
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if (CapHeaderId == CapId) {
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return CapHeaderOffset;
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}
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CapHeaderOffset = (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 2) >> 4);
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}
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return 0;
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}
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