/* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ROCKCHIP_SIP_H
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#define __ROCKCHIP_SIP_H
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#include <linux/arm-smccc.h>
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#include <linux/io.h>
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/* SMC function IDs for SiP Service queries, compatible with kernel-3.10 */
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#define SIP_ATF_VERSION 0x82000001
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#define SIP_ACCESS_REG 0x82000002
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#define SIP_SUSPEND_MODE 0x82000003
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#define SIP_PENDING_CPUS 0x82000004
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#define SIP_UARTDBG_CFG 0x82000005
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#define SIP_UARTDBG_CFG64 0xc2000005
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#define SIP_MCU_EL3FIQ_CFG 0x82000006
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#define SIP_ACCESS_CHIP_STATE64 0xc2000006
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#define SIP_SECURE_MEM_CONFIG 0x82000007
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#define SIP_ACCESS_CHIP_EXTRA_STATE64 0xc2000007
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#define SIP_DRAM_CONFIG 0x82000008
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#define SIP_SHARE_MEM 0x82000009
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#define SIP_SIP_VERSION 0x8200000a
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#define SIP_REMOTECTL_CFG 0x8200000b
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#define PSCI_SIP_VPU_RESET 0x8200000c
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#define SIP_BUS_CFG 0x8200000d
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#define SIP_LAST_LOG 0x8200000e
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#define SIP_SCMI_AGENT0 0x82000010
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#define SIP_SCMI_AGENT1 0x82000011
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#define SIP_SCMI_AGENT2 0x82000012
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#define SIP_SCMI_AGENT3 0x82000013
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#define SIP_SCMI_AGENT4 0x82000014
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#define SIP_SCMI_AGENT5 0x82000015
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#define SIP_SCMI_AGENT6 0x82000016
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#define SIP_SCMI_AGENT7 0x82000017
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#define SIP_SCMI_AGENT8 0x82000018
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#define SIP_SCMI_AGENT9 0x82000019
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#define SIP_SCMI_AGENT10 0x8200001a
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#define SIP_SCMI_AGENT11 0x8200001b
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#define SIP_SCMI_AGENT12 0x8200001c
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#define SIP_SCMI_AGENT13 0x8200001d
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#define SIP_SCMI_AGENT14 0x8200001e
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#define SIP_SCMI_AGENT15 0x8200001f
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#define SIP_SDEI_FIQ_DBG_SWITCH_CPU 0x82000020
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#define SIP_SDEI_FIQ_DBG_GET_EVENT_ID 0x82000021
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#define RK_SIP_AMP_CFG 0x82000022
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#define RK_SIP_FIQ_CTRL 0x82000024
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#define SIP_HDCP_CONFIG 0x82000025
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#define SIP_WDT_CFG 0x82000026
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#define SIP_HDMIRX_CFG 0x82000027
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#define SIP_MCU_CFG 0x82000028
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#define TRUSTED_OS_HDCPKEY_INIT 0xB7000003
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/* Rockchip Sip version */
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#define SIP_IMPLEMENT_V1 (1)
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#define SIP_IMPLEMENT_V2 (2)
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/* Trust firmware version */
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#define ATF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
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#define ATF_VER_MINOR(ver) (((ver) >> 0) & 0xffff)
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/* SIP_ACCESS_REG: read or write */
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#define SECURE_REG_RD 0x0
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#define SECURE_REG_WR 0x1
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/* Fiq debugger share memory: 8KB enough */
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#define FIQ_UARTDBG_PAGE_NUMS 2
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#define FIQ_UARTDBG_SHARE_MEM_SIZE ((FIQ_UARTDBG_PAGE_NUMS) * 4096)
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/* Error return code */
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#define IS_SIP_ERROR(x) (!!(x))
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#define SIP_RET_SUCCESS 0
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#define SIP_RET_SMC_UNKNOWN -1
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#define SIP_RET_NOT_SUPPORTED -2
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#define SIP_RET_INVALID_PARAMS -3
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#define SIP_RET_INVALID_ADDRESS -4
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#define SIP_RET_DENIED -5
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#define SIP_RET_SET_RATE_TIMEOUT -6
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/* SIP_UARTDBG_CFG64 call types */
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#define UARTDBG_CFG_INIT 0xf0
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#define UARTDBG_CFG_OSHDL_TO_OS 0xf1
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#define UARTDBG_CFG_OSHDL_CPUSW 0xf3
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#define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4
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#define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5
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#define UARTDBG_CFG_PRINT_PORT 0xf7
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#define UARTDBG_CFG_FIQ_ENABEL 0xf8
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#define UARTDBG_CFG_FIQ_DISABEL 0xf9
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/* SIP_SUSPEND_MODE32 call types */
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#define SUSPEND_MODE_CONFIG 0x01
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#define WKUP_SOURCE_CONFIG 0x02
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#define PWM_REGULATOR_CONFIG 0x03
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#define GPIO_POWER_CONFIG 0x04
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#define SUSPEND_DEBUG_ENABLE 0x05
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#define APIOS_SUSPEND_CONFIG 0x06
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#define VIRTUAL_POWEROFF 0x07
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#define SUSPEND_WFI_TIME_MS 0x08
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#define LINUX_PM_STATE 0x09
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#define SUSPEND_IO_RET_CONFIG 0x0a
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#define SLEEP_PIN_CONFIG 0x0b
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/* SIP_REMOTECTL_CFG call types */
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#define REMOTECTL_SET_IRQ 0xf0
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#define REMOTECTL_SET_PWM_CH 0xf1
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#define REMOTECTL_SET_PWRKEY 0xf2
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#define REMOTECTL_GET_WAKEUP_STATE 0xf3
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#define REMOTECTL_ENABLE 0xf4
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/* wakeup state */
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#define REMOTECTL_PWRKEY_WAKEUP 0xdeadbeaf
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/* SIP_MCU_CFG child configs, MCU ID */
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enum {
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RK_BUS_MCU,
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RK_PMU_MCU,
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RK_DDR_MCU,
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RK_NPU_MCU,
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};
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#define RK_SIP_MCU_ID(type, id) ((type) << 8 | id)
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#define RK_SIP_CFG_BUSMCU_0_ID RK_SIP_MCU_ID(RK_BUS_MCU, 0)
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#define RK_SIP_CFG_BUSMCU_1_ID RK_SIP_MCU_ID(RK_BUS_MCU, 1)
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#define RK_SIP_CFG_PMUMCU_0_ID RK_SIP_MCU_ID(RK_PMU_MCU, 0)
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#define RK_SIP_CFG_DDRMCU_0_ID RK_SIP_MCU_ID(RK_DDR_MCU, 0)
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#define RK_SIP_CFG_NPUMCU_0_ID RK_SIP_MCU_ID(RK_NPU_MCU, 0)
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/* SIP_MCU_CFG child configs */
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#define CONFIG_MCU_CODE_START_ADDR 0x01
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#define CONFIG_MCU_EXPERI_START_ADDR 0x02
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#define CONFIG_MCU_SRAM_START_ADDR 0x03
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#define CONFIG_MCU_EXSRAM_START_ADDR 0x04
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struct dram_addrmap_info {
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u64 ch_mask[2];
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u64 bk_mask[4];
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u64 bg_mask[2];
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u64 cs_mask[2];
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u32 reserved[20];
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u32 bank_bit_first;
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u32 bank_bit_mask;
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};
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/* AMP Ctrl */
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enum {
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RK_AMP_SUB_FUNC_CFG_MODE = 0,
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RK_AMP_SUB_FUNC_BOOT_ARG01,
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RK_AMP_SUB_FUNC_BOOT_ARG23,
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RK_AMP_SUB_FUNC_REQ_CPU_OFF,
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RK_AMP_SUB_FUNC_GET_CPU_STATUS,
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RK_AMP_SUB_FUNC_RSV, /* for RTOS */
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RK_AMP_SUB_FUNC_CPU_ON,
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RK_AMP_SUB_FUNC_END,
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};
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enum {
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FIRMWARE_NONE,
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FIRMWARE_TEE_32BIT,
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FIRMWARE_ATF_32BIT,
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FIRMWARE_ATF_64BIT,
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FIRMWARE_END,
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};
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/* Share mem page types */
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typedef enum {
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SHARE_PAGE_TYPE_INVALID = 0,
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SHARE_PAGE_TYPE_UARTDBG,
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SHARE_PAGE_TYPE_DDR,
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SHARE_PAGE_TYPE_DDRDBG,
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SHARE_PAGE_TYPE_DDRECC,
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SHARE_PAGE_TYPE_DDRFSP,
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SHARE_PAGE_TYPE_DDR_ADDRMAP,
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SHARE_PAGE_TYPE_LAST_LOG,
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SHARE_PAGE_TYPE_HDCP,
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SHARE_PAGE_TYPE_SLEEP,
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SHARE_PAGE_TYPE_MAX,
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} share_page_type_t;
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/* fiq control sub func */
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enum {
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RK_SIP_FIQ_CTRL_FIQ_EN = 1,
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RK_SIP_FIQ_CTRL_FIQ_DIS,
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RK_SIP_FIQ_CTRL_SET_AFF
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};
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/* hdcp function types */
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enum {
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HDCP_FUNC_STORAGE_INCRYPT = 1,
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HDCP_FUNC_KEY_LOAD,
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HDCP_FUNC_ENCRYPT_MODE
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};
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/* support hdcp device list */
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enum {
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DP_TX0,
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DP_TX1,
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EDP_TX0,
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EDP_TX1,
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HDMI_TX0,
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HDMI_TX1,
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HDMI_RX,
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MAX_DEVICE,
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};
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/* SIP_WDT_CONFIG call types */
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enum {
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WDT_START = 0,
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WDT_STOP = 1,
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WDT_PING = 2,
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};
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/* SIP_HDMIRX_CONFIG child configs */
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enum {
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HDMIRX_AUTO_TOUCH_EN = 0,
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HDMIRX_REG_PRE_FETCH = 1,
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HDMIRX_INFO_NOTIFY = 2,
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};
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struct pt_regs;
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typedef void (*sip_fiq_debugger_uart_irq_tf_cb_t)(struct pt_regs *_pt_regs, unsigned long cpu);
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/*
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* Rules: struct arm_smccc_res contains result and data, details:
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*
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* a0: error code(0: success, !0: error);
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* a1~a3: data
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*/
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#if IS_REACHABLE(CONFIG_ROCKCHIP_SIP)
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struct arm_smccc_res sip_smc_get_atf_version(void);
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struct arm_smccc_res sip_smc_get_sip_version(void);
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struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2);
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struct arm_smccc_res sip_smc_request_share_mem(u32 page_num,
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share_page_type_t page_type);
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struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg2);
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struct arm_smccc_res sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2);
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struct arm_smccc_res sip_smc_get_suspend_info(u32 info);
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struct arm_smccc_res sip_smc_lastlog_request(void);
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int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2);
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int sip_smc_virtual_poweroff(void);
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int sip_smc_remotectl_config(u32 func, u32 data);
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int sip_smc_secure_reg_write(u32 addr_phy, u32 val);
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u32 sip_smc_secure_reg_read(u32 addr_phy);
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struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2);
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struct dram_addrmap_info *sip_smc_get_dram_map(void);
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int sip_smc_amp_config(u32 sub_func_id, u32 arg1, u32 arg2, u32 arg3);
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struct arm_smccc_res sip_smc_get_amp_info(u32 sub_func_id, u32 arg1);
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void __iomem *sip_hdcp_request_share_memory(int id);
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struct arm_smccc_res sip_hdcp_config(u32 arg0, u32 arg1, u32 arg2);
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ulong sip_cpu_logical_map_mpidr(u32 cpu);
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/***************************fiq debugger **************************************/
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void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu);
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void sip_fiq_debugger_enable_debug(bool enable);
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int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, sip_fiq_debugger_uart_irq_tf_cb_t callback_fn);
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int sip_fiq_debugger_set_print_port(u32 port_phyaddr, u32 baudrate);
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int sip_fiq_debugger_request_share_memory(void);
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int sip_fiq_debugger_get_target_cpu(void);
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int sip_fiq_debugger_switch_cpu(u32 cpu);
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int sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu, u32 target_cpu, u32 flag);
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int sip_fiq_debugger_is_enabled(void);
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int sip_fiq_debugger_sdei_get_event_id(u32 *fiq, u32 *sw_cpu, u32 *flag);
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int sip_fiq_control(u32 sub_func, u32 irq, unsigned long data);
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int sip_wdt_config(u32 sub_func, u32 arg1, u32 arg2, u32 arg3);
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int sip_hdmirx_config(u32 sub_func, u32 arg1, u32 arg2, u32 arg3);
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int sip_hdcpkey_init(u32 hdcp_id);
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int sip_smc_mcu_config(unsigned long mcu_id, unsigned long func, unsigned long arg2);
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#else
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static inline struct arm_smccc_res sip_smc_get_atf_version(void)
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{
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struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
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return tmp;
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}
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static inline struct arm_smccc_res sip_smc_get_sip_version(void)
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{
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struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
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return tmp;
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}
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static inline struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2)
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{
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struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
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return tmp;
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}
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static inline struct arm_smccc_res sip_smc_request_share_mem
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(u32 page_num, share_page_type_t page_type)
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{
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struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
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return tmp;
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}
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static inline struct arm_smccc_res sip_smc_mcu_el3fiq
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(u32 arg0, u32 arg1, u32 arg2)
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{
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struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
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return tmp;
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}
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static inline struct arm_smccc_res
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sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2)
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{
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struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
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return tmp;
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}
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static inline struct arm_smccc_res sip_smc_get_suspend_info(u32 info)
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{
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struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
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return tmp;
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}
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static inline struct arm_smccc_res sip_smc_lastlog_request(void)
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{
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struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
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return tmp;
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}
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static inline int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2)
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{
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return 0;
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}
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static inline int sip_smc_virtual_poweroff(void) { return 0; }
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static inline int sip_smc_remotectl_config(u32 func, u32 data) { return 0; }
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static inline int sip_smc_secure_reg_write(u32 addr_phy, u32 val) { return 0; }
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static inline u32 sip_smc_secure_reg_read(u32 addr_phy) { return 0; }
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static inline struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2)
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{
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struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
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return tmp;
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}
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static inline struct dram_addrmap_info *sip_smc_get_dram_map(void)
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{
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return NULL;
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}
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static inline int sip_smc_amp_config(u32 sub_func_id,
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u32 arg1,
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u32 arg2,
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u32 arg3)
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{
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return 0;
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}
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static inline struct arm_smccc_res sip_smc_get_amp_info(u32 sub_func_id,
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u32 arg1)
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{
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struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED, };
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return tmp;
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}
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static inline void __iomem *sip_hdcp_request_share_memory(int id)
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{
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return NULL;
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}
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static inline struct arm_smccc_res sip_hdcp_config(u32 arg0, u32 arg1, u32 arg2)
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{
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struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
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return tmp;
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}
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static inline ulong sip_cpu_logical_map_mpidr(u32 cpu) { return 0; }
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/***************************fiq debugger **************************************/
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static inline void sip_fiq_debugger_enable_fiq
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(bool enable, uint32_t tgt_cpu) { return; }
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static inline void sip_fiq_debugger_enable_debug(bool enable) { return; }
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static inline int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id,
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sip_fiq_debugger_uart_irq_tf_cb_t callback_fn)
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{
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return 0;
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}
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static inline int sip_fiq_debugger_set_print_port(u32 port_phyaddr,
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u32 baudrate)
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{
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return 0;
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}
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static inline int sip_fiq_debugger_request_share_memory(void) { return 0; }
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static inline int sip_fiq_debugger_get_target_cpu(void) { return 0; }
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static inline int sip_fiq_debugger_switch_cpu(u32 cpu) { return 0; }
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static inline int sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu, u32 target_cpu,
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u32 flag) { return 0; }
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static inline int sip_fiq_debugger_is_enabled(void) { return 0; }
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static inline int sip_fiq_debugger_sdei_get_event_id(u32 *fiq, u32 *sw_cpu, u32 *flag)
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{
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return SIP_RET_NOT_SUPPORTED;
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}
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static inline int sip_fiq_control(u32 sub_func, u32 irq, unsigned long data)
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{
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return 0;
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}
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static inline int sip_wdt_config(u32 sub_func,
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u32 arg1,
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u32 arg2,
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u32 arg3)
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{
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return 0;
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}
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static inline int sip_hdmirx_config(u32 sub_func,
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u32 arg1,
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u32 arg2,
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u32 arg3)
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{
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return SIP_RET_NOT_SUPPORTED;
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}
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static inline int sip_hdcpkey_init(u32 hdcp_id)
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{
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return 0;
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}
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static inline int sip_smc_mcu_config(unsigned long mcu_id,
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unsigned long func,
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unsigned long arg2)
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{
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return SIP_RET_NOT_SUPPORTED;
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}
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#endif
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/* 32-bit OP-TEE context, never change order of members! */
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struct sm_nsec_ctx {
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u32 usr_sp;
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u32 usr_lr;
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u32 irq_spsr;
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u32 irq_sp;
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u32 irq_lr;
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u32 fiq_spsr;
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u32 fiq_sp;
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u32 fiq_lr;
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u32 svc_spsr;
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u32 svc_sp;
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u32 svc_lr;
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u32 abt_spsr;
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u32 abt_sp;
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u32 abt_lr;
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u32 und_spsr;
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u32 und_sp;
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u32 und_lr;
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u32 mon_lr;
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u32 mon_spsr;
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u32 r4;
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u32 r5;
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u32 r6;
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u32 r7;
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u32 r8;
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u32 r9;
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u32 r10;
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u32 r11;
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u32 r12;
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u32 r0;
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u32 r1;
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u32 r2;
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u32 r3;
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};
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/* 64-bit ATF context, never change order of members! */
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struct gp_regs_ctx {
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u64 x0;
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u64 x1;
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u64 x2;
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u64 x3;
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u64 x4;
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u64 x5;
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u64 x6;
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u64 x7;
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u64 x8;
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u64 x9;
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u64 x10;
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u64 x11;
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u64 x12;
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u64 x13;
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u64 x14;
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u64 x15;
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u64 x16;
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u64 x17;
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u64 x18;
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u64 x19;
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u64 x20;
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u64 x21;
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u64 x22;
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u64 x23;
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u64 x24;
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u64 x25;
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u64 x26;
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u64 x27;
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u64 x28;
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u64 x29;
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u64 lr;
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u64 sp_el0;
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u64 scr_el3;
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u64 runtime_sp;
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u64 spsr_el3;
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u64 elr_el3;
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};
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#endif
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