/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _IRQ_GENERIC_H
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#define _IRQ_GENERIC_H
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#include <asm-generic/gpio.h>
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#include <common.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#define IRQ_I(fmt, args...) printf("IRQ: "fmt, ##args)
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#define IRQ_W(fmt, args...) printf("IRQ Warn: "fmt, ##args)
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#define IRQ_E(fmt, args...) printf("IRQ Err: "fmt, ##args)
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#define IRQ_D(fmt, args...) debug("IRQ Debug "fmt, ##args)
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/*
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* IRQ line status.
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*
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* IRQ_TYPE_NONE - default, unspecified type
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* IRQ_TYPE_EDGE_RISING - rising edge triggered
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* IRQ_TYPE_EDGE_FALLING - falling edge triggered
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* IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
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* IRQ_TYPE_LEVEL_HIGH - high level triggered
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* IRQ_TYPE_LEVEL_LOW - low level triggered
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* IRQ_TYPE_LEVEL_MASK - mask to filter out the level bits
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* IRQ_TYPE_SENSE_MASK - mask for all the above bits
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*/
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enum {
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IRQ_TYPE_NONE = 0x00000000,
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IRQ_TYPE_EDGE_RISING = 0x00000001,
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IRQ_TYPE_EDGE_FALLING = 0x00000002,
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IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
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IRQ_TYPE_LEVEL_HIGH = 0x00000004,
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IRQ_TYPE_LEVEL_LOW = 0x00000008,
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IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
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IRQ_TYPE_SENSE_MASK = 0x0000000f,
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};
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/*
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* struct irq_chip - hardware interrupt chip descriptor
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*
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* @name: name for irq chip
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* @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
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* @irq_disable: disable the interrupt
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* @irq_ack: start of a new interrupt
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* @irq_eoi: end of interrupt
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* @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
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*/
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struct irq_chip {
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const char *name;
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int (*irq_init)(void);
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int (*irq_suspend)(void);
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int (*irq_resume)(void);
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int (*irq_get)(void);
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int (*irq_enable)(int irq);
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int (*irq_disable)(int irq);
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void (*irq_ack)(int irq);
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void (*irq_eoi)(int irq);
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int (*irq_set_type)(int irq, unsigned int flow_type);
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int (*irq_revert_type)(int irq);
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int (*irq_get_gpio_level)(int irq);
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};
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/*
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* Virtual irq chip structure
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*/
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typedef int(virq_write_t)(struct udevice *dev, uint reg, uint value);
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typedef int(virq_read_t)(struct udevice *dev, uint reg);
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struct virq_reg {
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uint reg_offset;
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uint mask;
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};
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struct virq_chip {
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uint status_base;
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uint mask_base;
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uint irq_reg_stride;
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uint irq_unalign_reg_idx;
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uint irq_unalign_reg_stride;
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int num_regs;
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const struct virq_reg *irqs;
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int num_irqs;
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virq_read_t *read;
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virq_write_t *write;
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};
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/* APIs for irqs */
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void irq_install_handler(int irq, interrupt_handler_t *handler, void *data);
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void irq_free_handler(int irq);
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int irq_set_irq_type(int irq, unsigned int type);
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int irq_revert_irq_type(int irq);
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int irq_handler_enable(int irq);
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int irq_handler_enable_suspend_only(int irq);
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int irq_handler_disable(int irq);
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int irq_get_gpio_level(int irq);
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int irqs_suspend(void);
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int irqs_resume(void);
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int irq_is_busy(int irq);
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int gpio_to_irq(struct gpio_desc *gpio);
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/*
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* Assign gpio to irq directly. Don't use it without special reasons.
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*
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* Usage example:
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* int gpio0_a0, irq;
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*
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* gpio = RK_IRQ_GPIO(RK_GPIO0, RK_PA0);
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* irq = hard_gpio_to_irq(gpio0_a0);
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* irq_install_handler(irq, ...);
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*/
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#define GPIO_BANK_SHIFT 8
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#define RK_IRQ_GPIO(bank, pin) (((bank) << GPIO_BANK_SHIFT) | (pin))
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int hard_gpio_to_irq(unsigned gpio);
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int phandle_gpio_to_irq(u32 gpio_phandle, u32 pin);
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/* Virtual irq */
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int virq_to_irq(struct virq_chip *chip, int virq);
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int virq_add_chip(struct udevice *dev, struct virq_chip *chip, int irq);
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#endif /* _IRQ_GENERIC_H */
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