// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Rockchip Electronics Co., Ltd.
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*/
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#if defined(CONFIG_ROCKCHIP_RV1126) || defined(CONFIG_ROCKCHIP_RK3568)
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#include <common.h>
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#include <console.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/sdram_common.h>
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#if defined(CONFIG_ROCKCHIP_RV1126)
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#include <asm/arch/sdram_rv1126.h>
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#elif defined(CONFIG_ROCKCHIP_RK3568)
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#include <asm/arch/sdram_rk3568.h>
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#endif
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#define __version__ "0.0.6"
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#define PRINT_LENGTH 64
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#ifndef PRINT_STEP
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#define PRINT_STEP 1
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#endif
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#define PRINT_RANGE ((PRINT_LENGTH) * (PRINT_STEP))
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struct print_border {
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u16 far_left;
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u16 far_right;
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};
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struct rw_trn_result result;
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static void calc_print_border(struct cs_rw_trn_result *result, u8 byte_en,
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u16 deskew_num, struct print_border *print_border)
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{
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u16 far_left = deskew_num;
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u16 far_right = 0;
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u16 mid;
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u8 dqs;
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u8 dq;
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if (deskew_num <= PRINT_RANGE) {
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print_border->far_left = 0;
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print_border->far_right = deskew_num - 1;
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return;
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}
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for (dqs = 0; dqs < BYTE_NUM; dqs++) {
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if ((byte_en & BIT(dqs)) == 0)
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continue;
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for (dq = 0; dq < 8; dq++) {
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if (result->dqs[dqs].dq_min[dq] < far_left)
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far_left = result->dqs[dqs].dq_min[dq];
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if (result->dqs[dqs].dq_max[dq] > far_right)
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far_right = result->dqs[dqs].dq_max[dq];
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}
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}
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if (far_right - far_left + 1 > PRINT_RANGE) {
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print_border->far_left = far_left & ~((u16)(PRINT_STEP * 4 - 1));
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print_border->far_right = far_right | (PRINT_STEP * 4 - 1);
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} else {
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mid = (far_left + far_right) / 2;
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if (mid < PRINT_RANGE / 2) {
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print_border->far_left = 0;
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print_border->far_right = PRINT_RANGE - 1;
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} else if (mid > deskew_num - PRINT_RANGE / 2) {
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print_border->far_left = deskew_num - PRINT_RANGE;
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print_border->far_right = deskew_num - 1;
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} else {
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print_border->far_left = mid - PRINT_RANGE / 2;
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print_border->far_right = mid + PRINT_RANGE / 2 - 1;
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}
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}
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}
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static void print_title_bar(struct print_border *print_border)
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{
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int i;
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printf(" ");
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for (i = print_border->far_left; i < print_border->far_right;
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i += PRINT_STEP * 4)
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printf("%-4d", i);
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printf(" Margin_L Sample Margin_R Width DQS\n");
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}
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static void print_ddr_dq_eye(struct fsp_rw_trn_result *fsp_result, u8 cs,
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u8 byte_en, u16 width_ref,
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struct print_border *print_border)
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{
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u16 sample;
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u16 min;
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u16 max;
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u16 dq_eye_width;
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u8 dqs;
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u8 dq;
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int i;
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struct cs_rw_trn_result *result = &fsp_result->cs[cs];
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for (dqs = 0; dqs < BYTE_NUM; dqs++) {
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if ((byte_en & BIT(dqs)) == 0)
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continue;
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for (dq = 0; dq < 8; dq++) {
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sample = fsp_result->min_val +
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result->dqs[dqs].dq_deskew[dq];
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min = result->dqs[dqs].dq_min[dq];
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max = result->dqs[dqs].dq_max[dq];
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dq_eye_width = max >= min ? max - min + 1 : 0;
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printf("DQ%-2d ", dqs * 8 + dq);
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for (i = print_border->far_left;
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i <= print_border->far_right; i += PRINT_STEP) {
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if (i / PRINT_STEP == sample / PRINT_STEP)
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printf("|");
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else if (i / PRINT_STEP >= min / PRINT_STEP &&
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i / PRINT_STEP <= max / PRINT_STEP)
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printf("*");
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else
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printf("-");
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}
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printf(" %5d%8d%8d",
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sample > min ? sample - min : 0, sample,
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max > sample ? max - sample : 0);
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if (dq_eye_width >= width_ref)
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printf("%8d%8d\n", dq_eye_width,
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fsp_result->min_val +
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result->dqs[dqs].dqs_deskew);
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else
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printf(" [%3d]%7d\n", dq_eye_width,
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fsp_result->min_val +
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result->dqs[dqs].dqs_deskew);
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}
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}
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printf("\n");
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}
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static u16 cs_eye_width_min(struct cs_rw_trn_result *result, u8 byte_en,
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u16 deskew_num)
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{
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u16 min;
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u16 max;
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u16 dq_eye_width;
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u16 cs_eye_width = deskew_num;
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u8 dqs;
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u8 dq;
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for (dqs = 0; dqs < BYTE_NUM; dqs++) {
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if ((byte_en & BIT(dqs)) == 0)
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continue;
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for (dq = 0; dq < 8; dq++) {
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min = result->dqs[dqs].dq_min[dq];
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max = result->dqs[dqs].dq_max[dq];
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dq_eye_width = max >= min ? max - min + 1 : 0;
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if (cs_eye_width > dq_eye_width)
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cs_eye_width = dq_eye_width;
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}
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}
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return cs_eye_width;
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}
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static int do_ddr_dq_eye(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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unsigned long freq_mhz;
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u32 ddr_type;
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u16 rd_width = RD_DESKEW_NUM;
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u16 wr_width = WR_DESKEW_NUM;
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u16 cs_eye_width;
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u16 rd_width_ref;
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u16 wr_width_ref;
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u16 width_ref_mhz;
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u8 fsp = 0;
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u8 cs;
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int i;
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struct print_border print_border;
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printf("Rockchip DDR DQ Eye Tool v" __version__ "\n");
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#if defined(CONFIG_ROCKCHIP_RV1126)
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ddr_type = (readl(0xfe020208) >> 13) & 0x7;
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#elif defined(CONFIG_ROCKCHIP_RK3568)
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ddr_type = ((readl(0xfdc2020c) & (0x3 << 12)) >> 9) |
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((readl(0xfdc20208) >> 13) & 0x7);
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#else
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printf("Rockchip DDR DQ Eye Tool only support RK3568/RK3566 and RV1126 now.\n");
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return CMD_RET_FAILURE;
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#endif
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if (readl(RW_TRN_RESULT_ADDR) == DDR_DQ_EYE_FLAG) {
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memcpy(&result, (void *)(RW_TRN_RESULT_ADDR), sizeof(result));
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} else {
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printf("Fail to get data of DDR DQ eye.\n");
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printf("Please update the Loader.\n");
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return CMD_RET_FAILURE;
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}
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if (argc == 1) {
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/* use the max freq if no arg */
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for (i = 0; i < FSP_NUM; i++) {
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if (result.fsp_mhz[i] > result.fsp_mhz[fsp])
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fsp = i;
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}
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} else if (argc > 1) {
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if (strict_strtoul(argv[1], 0, &freq_mhz) < 0)
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return CMD_RET_USAGE;
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if (freq_mhz >= 0 && freq_mhz < FSP_NUM) {
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/* when user enter the fsp rather than the freq_mhz */
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fsp = (u8)freq_mhz;
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} else {
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for (fsp = 0; fsp < FSP_NUM; fsp++)
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if (result.fsp_mhz[fsp] == freq_mhz ||
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result.fsp_mhz[fsp] == (u16)(freq_mhz / MHZ))
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break;
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if (fsp >= FSP_NUM)
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return CMD_RET_USAGE;
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}
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} else {
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return CMD_RET_FAILURE;
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}
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printf("DDR type: ");
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switch (ddr_type) {
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case LPDDR4X:
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if (result.fsp_mhz[fsp] <
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(LP4_WIDTH_REF_MHZ_L + LP4_WIDTH_REF_MHZ_H) / 2) {
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rd_width_ref = LP4_RD_WIDTH_REF_L;
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wr_width_ref = LP4_WR_WIDTH_REF_L;
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width_ref_mhz = LP4_WIDTH_REF_MHZ_L;
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} else {
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rd_width_ref = LP4_RD_WIDTH_REF_H;
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wr_width_ref = LP4_WR_WIDTH_REF_H;
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width_ref_mhz = LP4_WIDTH_REF_MHZ_H;
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}
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printf("LPDDR4X");
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break;
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case LPDDR4:
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if (result.fsp_mhz[fsp] <
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(LP4_WIDTH_REF_MHZ_L + LP4_WIDTH_REF_MHZ_H) / 2) {
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rd_width_ref = LP4_RD_WIDTH_REF_L;
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wr_width_ref = LP4_WR_WIDTH_REF_L;
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width_ref_mhz = LP4_WIDTH_REF_MHZ_L;
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} else {
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rd_width_ref = LP4_RD_WIDTH_REF_H;
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wr_width_ref = LP4_WR_WIDTH_REF_H;
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width_ref_mhz = LP4_WIDTH_REF_MHZ_H;
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}
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printf("LPDDR4");
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break;
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case LPDDR3:
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if (result.fsp_mhz[fsp] <
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(LP4_WIDTH_REF_MHZ_L + LP4_WIDTH_REF_MHZ_H) / 2) {
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rd_width_ref = LP3_RD_WIDTH_REF_L;
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wr_width_ref = LP3_WR_WIDTH_REF_L;
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width_ref_mhz = LP3_WIDTH_REF_MHZ_L;
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} else {
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rd_width_ref = LP3_RD_WIDTH_REF_H;
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wr_width_ref = LP3_WR_WIDTH_REF_H;
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width_ref_mhz = LP3_WIDTH_REF_MHZ_H;
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}
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printf("LPDDR3");
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break;
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case DDR4:
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if (result.fsp_mhz[fsp] <
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(DDR4_WIDTH_REF_MHZ_L + DDR4_WIDTH_REF_MHZ_H) / 2) {
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rd_width_ref = DDR4_RD_WIDTH_REF_L;
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wr_width_ref = DDR4_WR_WIDTH_REF_L;
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width_ref_mhz = DDR4_WIDTH_REF_MHZ_L;
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} else {
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rd_width_ref = DDR4_RD_WIDTH_REF_H;
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wr_width_ref = DDR4_WR_WIDTH_REF_H;
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width_ref_mhz = DDR4_WIDTH_REF_MHZ_H;
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}
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printf("DDR4");
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break;
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case DDR3:
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default:
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if (result.fsp_mhz[fsp] <
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(DDR3_WIDTH_REF_MHZ_L + DDR3_WIDTH_REF_MHZ_H) / 2) {
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rd_width_ref = DDR3_RD_WIDTH_REF_L;
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wr_width_ref = DDR3_WR_WIDTH_REF_L;
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width_ref_mhz = DDR3_WIDTH_REF_MHZ_L;
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} else {
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rd_width_ref = DDR3_RD_WIDTH_REF_H;
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wr_width_ref = DDR3_WR_WIDTH_REF_H;
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width_ref_mhz = DDR3_WIDTH_REF_MHZ_H;
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}
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printf("DDR3");
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break;
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} /* switch (ddr_type) */
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printf("\n");
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for (cs = 0; cs < result.cs_num; cs++) {
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calc_print_border(&result.rd_fsp[fsp].cs[cs], result.byte_en,
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RD_DESKEW_NUM, &print_border);
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printf("CS%d %dMHz read DQ eye:\n", cs, result.fsp_mhz[fsp]);
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print_title_bar(&print_border);
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print_ddr_dq_eye(&result.rd_fsp[fsp], cs, result.byte_en,
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rd_width_ref, &print_border);
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cs_eye_width = cs_eye_width_min(&result.rd_fsp[fsp].cs[cs],
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result.byte_en, RD_DESKEW_NUM);
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if (rd_width > cs_eye_width)
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rd_width = cs_eye_width;
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printf("CS%d %dMHz write DQ eye:\n", cs, result.fsp_mhz[fsp]);
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calc_print_border(&result.wr_fsp[fsp].cs[cs], result.byte_en,
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WR_DESKEW_NUM, &print_border);
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print_title_bar(&print_border);
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print_ddr_dq_eye(&result.wr_fsp[fsp], cs, result.byte_en,
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wr_width_ref, &print_border);
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cs_eye_width = cs_eye_width_min(&result.wr_fsp[fsp].cs[cs],
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result.byte_en, WR_DESKEW_NUM);
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if (wr_width > cs_eye_width)
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wr_width = cs_eye_width;
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}
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printf("DQ eye width min: %d(read), %d(write)\n", rd_width, wr_width);
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printf("DQ eye width reference: %d(read), %d(write) in %dMHz\n",
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rd_width_ref, wr_width_ref, width_ref_mhz);
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if (rd_width < rd_width_ref || wr_width < wr_width_ref)
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printf("ERROR: DQ eye width may be unreliable, please check!\n");
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return CMD_RET_SUCCESS;
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}
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U_BOOT_CMD(ddr_dq_eye, 2, 1, do_ddr_dq_eye,
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"Rockchip DDR DQ Eye Tool\n",
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"arg1: DDR freq in MHz, null for the max freq.\n"
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"example:\n"
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" ddr_dq_eye 1056: show the DDR DQ eye in 1056MHz."
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);
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#endif /* if defined(CONFIG_ROCKCHIP_RV1126) || defined(CONFIG_ROCKCHIP_RK3568) */
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