~ljy/RK3588_XEN.git

2024-11-01 7e970c18f85f99acc678d90128b6e01dce1bf273
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è§þÿÿéÄ½ìÿÿHìÿÿH@H¦H¦H5²*HÇèÕtÿÿÀËHn¦H5*HÇè·tÿÿÀHP¦H5*HÇètÿÿÀH2¦H5l*HÇè{tÿÿÀqH¦H5U*HÇè]tÿÿÀSHö¥H5>*HÇè?tÿÿÀ5HØ¥H5(*HÇè!tÿÿÀHº¥H5*HÇètÿÿÀùH¥H5ü)HÇèåsÿÿÀÛH~¥H5å)HÇèÇsÿÿÀ½H`¥H5Î)HÇè©sÿÿÀHB¥H5´)HÇèsÿÿÀH$¥H5)HÇèmsÿÿÀcH¥H5)HÇèOsÿÿÀEHè¤H5q)HÇè1sÿÿÀ'HÊ¤H5Z)HÇèsÿÿÀ    H¬¤H5A)HÇèõrÿÿÀëH¤H5+)HÇè×rÿÿÀÍHp¤H5)HÇè¹rÿÿÀ¯HR¤H5ü(HÇèrÿÿÀH4¤H5å(HÇè}rÿÿÀsH¤H5Ø$HÇè_rÿÿÀUHø£H5°(HÇèArÿÿÀ7HÚ£H5(HÇè#rÿÿÀH¼£H5(HÇèrÿÿÀûH£H5g$HÇèçqÿÿÀÝH£H5P$HÇèÉqÿÿÀ¿Hb£H59$HÇè«qÿÿÀ¡HD£H5(HÇèqÿÿÀH&£H5ú'HÇèoqÿÿÀtiH£H5ç'HÇèUqÿÿÀtOHò¢H5;HÇè;qÿÿÀt5HØ¢H5º'HÇè!qÿÿÀtH=®'èqpÿÿè¤úÿÿ¿èbqÿÿH£¢HÆH='¸èpÿÿ½ìÿÿLHìÿÿHÀHH5v'HÇèÝpÿÿH@ìÿÿH½@ìÿÿu'HìÿÿHÀHHÆH=G'¸è:pÿÿé?HìÿÿHÀHH54'HÇèpÿÿHHìÿÿH½Hìÿÿu6HìÿÿHÀHHÆH=ò&¸èåoÿÿH@ìÿÿHÇè¦oÿÿéÛHìÿÿHÀHH5-&HÇèpÿÿHXìÿÿH½XìÿÿuHHìÿÿHÀHH5&HÇèVpÿÿHXìÿÿH½XìÿÿuH5&H=§¢è2pÿÿHXìÿÿH½Xìÿÿ(Ç(ìÿÿé½ìÿÿHìÿÿHÀ HH50&HÇèoÿÿHHìÿÿH½Hìÿÿu'HìÿÿHÀ HHÆH=î%¸èánÿÿéæH5HÇèínÿÿëi½8ìÿÿguQÇ8HH5É%HÇèoÿÿHPìÿÿH½Pìÿÿu/Hò~HÆH=%¸èvnÿÿé{èTøÿÿ¿èoÿÿHìÿÿìÿÿHp%HÎÇèÄnÿÿ8ìÿÿ½8ìÿÿÿfÿÿÿë
èøÿÿé/Çìÿÿë#ìÿÿHH¤~Çìÿÿ½ìÿÿvÑd~øHìÿÿHhìÿÿH@ìÿÿHÂ¾H=÷ èòmÿÿHÀ·ÇìÿÿéìÿÿHÅHÅnHHÆH=· èBnÿÿHXìÿÿH½XìÿÿIH5|$H= ènÿÿH`ìÿÿH½`ìÿÿtH`ìÿÿH;Xìÿÿ¾=H=Y èmÿÿHXìÿÿH½Xìÿÿu2ìÿÿHÅH.nHHÆH=    $¸èÖlÿÿéÁHXìÿÿHXìÿÿ¶<
uCHXìÿÿHÀ¶Àu1HXìÿÿ¶¾À ìÿÿìÿÿHH!}Çë;HXìÿÿº¾HÇèïlÿÿ ìÿÿìÿÿHHä|ÇìÿÿHHhìÿÿHÂ ìÿÿ,ìÿÿëëìÿÿ3m9ìÿÿ]þÿÿé%þÿÿ½,ìÿÿuH=##èkÿÿé¦ÇìÿÿxV4Ç$ìÿÿHHìÿÿHìÿÿHÑº¾HÇè`kÿÿ ìÿÿ$ìÿÿ½ ìÿÿuìÿÿìÿÿ9Âu·HHìÿÿHÁº¾H=?èkÿÿHøtH=¤"èøjÿÿé.ÆH="¸è*kÿÿøw'$ìÿÿÀÁHHìÿÿºHÎHÇè]kÿÿéÒøt!Çøt¼øt±øuEÇ<ìÿÿµ<ìÿÿHHìÿÿHpìÿÿHÑºHÇè^jÿÿHøt"H="è<jÿÿérH="è+jÿÿéa=PLìÿÿ$ìÿÿHÐýÿÿHµpìÿÿHHìÿÿMÁAøHÇèàèÿÿÀ> H½ìÿÿHpìÿÿHµÐýÿÿH ôÿÿIøHÇèElÿÿzøuEÚH ôÿÿHPìÿÿHÎHÇèèðÿÿÀuH=v!èiÿÿéH=!èpiÿÿén=H°ûÿÿHpìÿÿHµ ôÿÿHìÿÿAøHÇèæÿÿhøÃ½(ìÿÿu`$ìÿÿÀÁHHìÿÿºHÎHÇè´iÿÿHHìÿÿH°ûÿÿHÑº¾(HÇèñiÿÿHøÎH=ô èËhÿÿé½$ìÿÿÀÁHHìÿÿºHÎHÇèTiÿÿHHìÿÿH°ûÿÿHzHÁº¾èiÿÿHøtqH= ènhÿÿëcøt!øtøtuøu7DiH½ìÿÿHpìÿÿH°ûÿÿµ$ìÿÿHHìÿÿEÁIøHÇèÝÿÿH=: èýgÿÿH½PìÿÿtHPìÿÿHÇèhÿÿëH½@ìÿÿtH@ìÿÿHÇèègÿÿëH½HìÿÿtHHìÿÿHÇèÌgÿÿëë¸HMødH3%(tè½gÿÿÉÃóúUHåHìÀH½HÿÿÿHµ@ÿÿÿdH%(HEø1ÀHÇ`ÿÿÿHÇhÿÿÿHpÿÿÿ¸¹H×óH«H@ÿÿÿ%ÿXÿÿÿ½XÿÿÿGH@ÿÿÿHÀH`ÿÿÿÇTÿÿÿëV¸+TÿÿÿÁà\ÿÿÿTÿÿÿÁèÀHH`ÿÿÿHÐ\ÿÿÿÁÓêÐ¶ÐTÿÿÿpÿÿÿTÿÿÿ½Tÿÿÿv¡HHÿÿÿH\H`ÿÿÿHpÿÿÿHhÿÿÿÇTÿÿÿëcTÿÿÿHÅH!eÀHHhÿÿÿHÐTÿÿÿHÕHùdÒHH`ÿÿÿHÊTÿÿÿ½TÿÿÿvH@ÿÿÿHÀ,H`ÿÿÿÇTÿÿÿëV¸+TÿÿÿÁà\ÿÿÿTÿÿÿÁèÀHH`ÿÿÿHÐ\ÿÿÿÁÓêÐ¶ÐTÿÿÿpÿÿÿTÿÿÿ½Tÿÿÿv¡HHÿÿÿHÜH`ÿÿÿHpÿÿÿHhÿÿÿÇTÿÿÿëcTÿÿÿHÅH
eÀHHhÿÿÿHÐTÿÿÿHÕHâdÒHH`ÿÿÿHÊTÿÿÿ½TÿÿÿvH@ÿÿÿHÀPH`ÿÿÿÇTÿÿÿëV¸+TÿÿÿÁà\ÿÿÿTÿÿÿÁèÀHH`ÿÿÿHÐ\ÿÿÿÁÓêÐ¶ÐTÿÿÿpÿÿÿTÿÿÿ½Tÿÿÿv¡HHÿÿÿH`H`ÿÿÿHpÿÿÿHhÿÿÿÇTÿÿÿëcTÿÿÿHÅHódÀHHhÿÿÿHÐTÿÿÿHÕHËdÒHH`ÿÿÿHÊTÿÿÿ½Tÿÿÿvë XÿÿÿÆH=¸èdÿÿ¸ÿÿÿÿë¸HuødH34%(tèÁcÿÿÉÃóúUHåHìÀH½HÿÿÿHµ@ÿÿÿdH%(HEø1ÀHÇ`ÿÿÿHÇhÿÿÿHpÿÿÿ¸¹H×óH«H@ÿÿÿ%ÿ\ÿÿÿ½\ÿÿÿñHHÿÿÿH\H`ÿÿÿHpÿÿÿHhÿÿÿÇXÿÿÿëcXÿÿÿHÅH¦aÀHH`ÿÿÿHÐXÿÿÿHÕHvaÒHHhÿÿÿHÊXÿÿÿ½XÿÿÿvH@ÿÿÿHÀH`ÿÿÿÇXÿÿÿé¿XÿÿÿÁàÀpÿÿÿÀtTXÿÿÿHH`ÿÿÿHÐ%ÿÿÿÁXÿÿÿÁàÀpÿÿÿÁàÂXÿÿÿH4H`ÿÿÿHð    ÊXÿÿÿÁàÀÀpÿÿÿÀt\XÿÿÿHH`ÿÿÿHÐ%ÿÿÿÁXÿÿÿÁàÀÀpÿÿÿÁà%ÿÂXÿÿÿH4H`ÿÿÿHð    ÊXÿÿÿÁàÀÀpÿÿÿÀtUXÿÿÿHH`ÿÿÿHÐ0äÁXÿÿÿÁàÀÀpÿÿÿÁà·ÐXÿÿÿH4H`ÿÿÿHð    ÊXÿÿÿÁàÀÀpÿÿÿÀtRXÿÿÿHH`ÿÿÿHÐ°ÁXÿÿÿÁàÀÀpÿÿÿ¶ÐXÿÿÿH4H`ÿÿÿHð    ÊXÿÿÿ½Xÿÿÿ4þÿÿÇXÿÿÿëXÿÿÿÇpÿÿÿXÿÿÿ½XÿÿÿvßHHÿÿÿHÜH`ÿÿÿHpÿÿÿHhÿÿÿÇXÿÿÿëcXÿÿÿHÅHò_ÀHH`ÿÿÿHÐXÿÿÿHÕHÂ_ÒHHhÿÿÿHÊXÿÿÿ½XÿÿÿvH@ÿÿÿHÀ,H`ÿÿÿÇXÿÿÿé¿XÿÿÿÁàÀpÿÿÿÀtTXÿÿÿHH`ÿÿÿHÐ%ÿÿÿÁXÿÿÿÁàÀpÿÿÿÁàÂXÿÿÿH4H`ÿÿÿHð    ÊXÿÿÿÁàÀÀpÿÿÿÀt\XÿÿÿHH`ÿÿÿHÐ%ÿÿÿÁXÿÿÿÁàÀÀpÿÿÿÁà%ÿÂXÿÿÿH4H`ÿÿÿHð    ÊXÿÿÿÁàÀÀpÿÿÿÀtUXÿÿÿHH`ÿÿÿHÐ0äÁXÿÿÿÁàÀÀpÿÿÿÁà·ÐXÿÿÿH4H`ÿÿÿHð    ÊXÿÿÿÁàÀÀpÿÿÿÀtRXÿÿÿHH`ÿÿÿHÐ°ÁXÿÿÿÁàÀÀpÿÿÿ¶ÐXÿÿÿH4H`ÿÿÿHð    ÊXÿÿÿ½Xÿÿÿ4þÿÿÇXÿÿÿëXÿÿÿÇpÿÿÿXÿÿÿ½XÿÿÿvßHHÿÿÿH`H`ÿÿÿHpÿÿÿHhÿÿÿÇXÿÿÿëcXÿÿÿHÅH>^ÀHH`ÿÿÿHÐXÿÿÿHÕH^ÒHHhÿÿÿHÊXÿÿÿ½XÿÿÿvH@ÿÿÿHÀPH`ÿÿÿÇXÿÿÿé¿XÿÿÿÁàÀpÿÿÿÀtTXÿÿÿHH`ÿÿÿHÐ%ÿÿÿÁXÿÿÿÁàÀpÿÿÿÁàÂXÿÿÿH4H`ÿÿÿHð    ÊXÿÿÿÁàÀÀpÿÿÿÀt\XÿÿÿHH`ÿÿÿHÐ%ÿÿÿÁXÿÿÿÁàÀÀpÿÿÿÁà%ÿÂXÿÿÿH4H`ÿÿÿHð    ÊXÿÿÿÁàÀÀpÿÿÿÀtUXÿÿÿHH`ÿÿÿHÐ0äÁXÿÿÿÁàÀÀpÿÿÿÁà·ÐXÿÿÿH4H`ÿÿÿHð    ÊXÿÿÿÁàÀÀpÿÿÿÀtRXÿÿÿHH`ÿÿÿHÐ°ÁXÿÿÿÁàÀÀpÿÿÿ¶ÐXÿÿÿH4H`ÿÿÿHð    ÊXÿÿÿ½Xÿÿÿ4þÿÿë \ÿÿÿÆH=]¸è[[ÿÿ¸ÿÿÿÿëH}ødH3<%(tè [ÿÿÉÃf.@óúAWL=VAVIÖAUIõATAüUH-|VSL)ýHìè?YÿÿHÁýt1ÛLòLîDçAÿßHÃH9ÝuêHÄ[]A\A]A^A_Ãff.óúÃóúHìHÄÃrk3528error: ca skew read out error for rk3528!write global info to bin file failwrite ddr2 info to bin file failwrite ddr3 info to bin file failwrite ddr4 info to bin file failnot support ddr5write lpddr2 info to bin file failwrite lpddr3 info to bin file failwrite bin lpddr4 info to file failwrite dq map to bin file failwrite bin lpddr4x info to file failwrite bin lpddr5 info to file failwrite bin skew info to file failwrite bin hash info to file fail
new bin config:_skew%s: %u
%s: 0x%x
read bin file failread global info from bin file failread ddr2 info from bin file failread ddr3 info from bin file failread ddr4 info from bin file failread lp2 info from bin file failread lp3 info from bin file failread lp4 info from bin file failread lpddr5 info from bin file failread skew verison from bin file failread rk3528_skew from bin file failread lp4x info from bin file failread ddr hash info from bin file failstart tag=0x12345678
_mappstore_maskskew_freq_mhz%d0x%xend
rv1126rk3566rk3568rk356xFor more details, please refer to the ddrbin_tool_user_guide.txt
This tools support two functions
for example:
function 1: modify ddr.bin file from ddrbin_param.txt.
    1) modify 'ddrbin_param.txt', set ddr frequency, uart info etc what you want.
    If want to keep items default, please keep these items blank.
    like: ./ddrbin_tool px30 ddrbin_param.txt px30_ddr_333MHz_v1.13.bin
 
function 2: get ddr.bin file config to gen_param.txt file
    If want to get ddrbin file config, please run like that:
    ./ddrbin_tool px30 -g gen_param.txt px30_ddr_333MHz_v1.15.bin
    The config will show in gen_param.txt.
 
Note:    The function 1 and function 2 are two separate functions
The gen_param.txt file which is generated by function 2 is no need used in function 1.
 
For more details, please refer to the ddrbin_tool_user_guide.txtversion v1.18 20230919rk312xrk3126px3serk3128rk322xrk3128hrk3228ark3228brk3229rk3368px5rk322xhrk3228hrk3328rk3326px30rk3326spx30srk3399rk3288rk1808rv1109rk3308rv1108rk3588rv1106rv1103rk3562chip name errorchip %s
ropen %s failed!
rb+rk3318w+g:h/*%s have no '=' value!!!
read param file failget version failversion %d
readout index failversion not supportgenerate info from bin file ok.generate info fail.write bin file failmodify endrk3528 ca skew sub version %x, Not support!!!
start tagddr2_freqlp2_freqddr3_freqlp3_freqddr4_freqlp4_freqlp4x_freqlp5_frequart iduart iomuxuart baudratesr_idlepd_idlefirst scan channelchannel maskstride typestandby_idleext_temp_reflink_ecc_enper_bank_ref_enderate_enauto_precharge_enres_space_remap_allres_space_remap_portionrd_vref_scan_enwr_vref_scan_eneye_2d_scan_endis_train_printssmod_downspreadssmod_divssmod_spreadddr_2tpstore_base_addrpstore_buf_sizeuboot_log_enatf_log_enoptee_log_enspl_log_entpl_log_enfirst_init_dram_typedfs_disablepagecloseboot_fspddr2_f1_freq_mhzddr2_f2_freq_mhzddr2_f3_freq_mhzddr2_f4_freq_mhzddr2_f5_freq_mhzphy_ddr2_dq_drv_when_odten_ohmphy_ddr2_ca_drv_when_odten_ohmphy_ddr2_clk_drv_when_odten_ohmddr2_dq_drv_when_odten_ohmphy_ddr2_dq_drv_when_odtoff_ohmphy_ddr2_ca_drv_when_odtoff_ohmphy_ddr2_clk_drv_when_odtoff_ohmddr2_dq_drv_when_odtoff_ohmphy_ddr2_odt_ohmddr2_odt_ohmphy_ddr2_odt_pull_up_enphy_ddr2_odt_pull_dn_enphy_ddr2_odten_freq_mhzddr2_odten_freq_mhzphy_ddr2_dq_sr_when_odtenphy_ddr2_ca_sr_when_odtenphy_ddr2_clk_sr_when_odtenphy_ddr2_dq_sr_when_odtoffphy_ddr2_ca_sr_when_odtoffphy_ddr2_clk_sr_when_odtoffphy_ddr2_dq_vref_when_odtenddr2_dq_vref_when_odtenddr2_ca_vref_when_odtenphy_ddr2_dq_vref_when_odtoffddr2_dq_vref_when_odtoffddr2_ca_vref_when_odtoffddr3_f1_freq_mhzddr3_f2_freq_mhzddr3_f3_freq_mhzddr3_f4_freq_mhzddr3_f5_freq_mhzphy_ddr3_dq_drv_when_odten_ohmphy_ddr3_ca_drv_when_odten_ohmphy_ddr3_clk_drv_when_odten_ohmddr3_dq_drv_when_odten_ohmphy_ddr3_dq_drv_when_odtoff_ohmphy_ddr3_ca_drv_when_odtoff_ohmphy_ddr3_clk_drv_when_odtoff_ohmddr3_dq_drv_when_odtoff_ohmphy_ddr3_odt_ohmddr3_odt_ohmphy_ddr3_odt_pull_up_enphy_ddr3_odt_pull_dn_enphy_ddr3_odten_freq_mhzddr3_odten_freq_mhzphy_ddr3_dq_sr_when_odtenphy_ddr3_ca_sr_when_odtenphy_ddr3_clk_sr_when_odtenphy_ddr3_dq_sr_when_odtoffphy_ddr3_ca_sr_when_odtoffphy_ddr3_clk_sr_when_odtoffphy_ddr3_dq_vref_when_odtenddr3_dq_vref_when_odtenddr3_ca_vref_when_odtenphy_ddr3_dq_vref_when_odtoffddr3_dq_vref_when_odtoffddr3_ca_vref_when_odtoffddr4_f1_freq_mhzddr4_f2_freq_mhzddr4_f3_freq_mhzddr4_f4_freq_mhzddr4_f5_freq_mhzphy_ddr4_dq_drv_when_odten_ohmphy_ddr4_ca_drv_when_odten_ohmphy_ddr4_clk_drv_when_odten_ohmddr4_dq_drv_when_odten_ohmphy_ddr4_dq_drv_when_odtoff_ohmphy_ddr4_ca_drv_when_odtoff_ohmphy_ddr4_clk_drv_when_odtoff_ohmddr4_dq_drv_when_odtoff_ohmphy_ddr4_odt_ohmddr4_odt_ohmphy_ddr4_odt_pull_up_enphy_ddr4_odt_pull_dn_enphy_ddr4_odten_freq_mhzddr4_odten_freq_mhzphy_ddr4_dq_sr_when_odtenphy_ddr4_ca_sr_when_odtenphy_ddr4_clk_sr_when_odtenphy_ddr4_dq_sr_when_odtoffphy_ddr4_ca_sr_when_odtoffphy_ddr4_clk_sr_when_odtoffphy_ddr4_dq_vref_when_odtenddr4_dq_vref_when_odtenddr4_ca_vref_when_odtenphy_ddr4_dq_vref_when_odtoffddr4_dq_vref_when_odtoffddr4_ca_vref_when_odtofflp2_f1_freq_mhzlp2_f2_freq_mhzlp2_f3_freq_mhzlp2_f4_freq_mhzlp2_f5_freq_mhzphy_lp2_dq_drv_when_odten_ohmphy_lp2_ca_drv_when_odten_ohmphy_lp2_clk_drv_when_odten_ohmlp2_dq_drv_when_odten_ohmphy_lp2_dq_drv_when_odtoff_ohmphy_lp2_ca_drv_when_odtoff_ohmphy_lp2_clk_drv_when_odtoff_ohmlp2_dq_drv_when_odtoff_ohmphy_lp2_odt_ohmlp2_odt_ohmphy_lp2_odt_pull_up_enphy_lp2_odt_pull_dn_enphy_lp2_odten_freq_mhzlp2_odten_freq_mhzphy_lp2_dq_sr_when_odtenphy_lp2_ca_sr_when_odtenphy_lp2_clk_sr_when_odtenphy_lp2_dq_sr_when_odtoffphy_lp2_ca_sr_when_odtoffphy_lp2_clk_sr_when_odtoffphy_lp2_dq_vref_when_odtenlp2_dq_vref_when_odtenlp2_ca_vref_when_odtenphy_lp2_dq_vref_when_odtofflp2_dq_vref_when_odtofflp2_ca_vref_when_odtofflp3_f1_freq_mhzlp3_f2_freq_mhzlp3_f3_freq_mhzlp3_f4_freq_mhzlp3_f5_freq_mhzphy_lp3_dq_drv_when_odten_ohmphy_lp3_ca_drv_when_odten_ohmphy_lp3_clk_drv_when_odten_ohmlp3_dq_drv_when_odten_ohmphy_lp3_dq_drv_when_odtoff_ohmphy_lp3_ca_drv_when_odtoff_ohmphy_lp3_clk_drv_when_odtoff_ohmlp3_dq_drv_when_odtoff_ohmphy_lp3_odt_ohmlp3_odt_ohmphy_lp3_odt_pull_up_enphy_lp3_odt_pull_dn_enphy_lp3_odten_freq_mhzlp3_odten_freq_mhzphy_lp3_dq_sr_when_odtenphy_lp3_ca_sr_when_odtenphy_lp3_clk_sr_when_odtenphy_lp3_dq_sr_when_odtoffphy_lp3_ca_sr_when_odtoffphy_lp3_clk_sr_when_odtoffphy_lp3_dq_vref_when_odtenlp3_dq_vref_when_odtenlp3_ca_vref_when_odtenphy_lp3_dq_vref_when_odtofflp3_dq_vref_when_odtofflp3_ca_vref_when_odtofflp4_f1_freq_mhzlp4_f2_freq_mhzlp4_f3_freq_mhzlp4_f4_freq_mhzlp4_f5_freq_mhzphy_lp4_dq_drv_when_odten_ohmphy_lp4_ca_drv_when_odten_ohmphy_lp4_clk_drv_when_odten_ohmlp4_dq_drv_when_odten_ohmphy_lp4_dq_drv_when_odtoff_ohmphy_lp4_ca_drv_when_odtoff_ohmphy_lp4_clk_drv_when_odtoff_ohmlp4_dq_drv_when_odtoff_ohmphy_lp4_odt_ohmlp4_odt_ohmlp4_ca_odt_ohmlp4_drv_pu_cal_odtenlp4_drv_pu_cal_odtoffphy_lp4_drv_pull_dn_en_odtenphy_lp4_drv_pull_dn_en_odtoffphy_lp4_odten_freq_mhzlp4_dq_odten_freq_mhzphy_lp4_dq_sr_when_odtenphy_lp4_ca_sr_when_odtenphy_lp4_clk_sr_when_odtenphy_lp4_dq_sr_when_odtoffphy_lp4_ca_sr_when_odtoffphy_lp4_clk_sr_when_odtofflp4_ca_odten_freq_mhzphy_lp4_cs_drv_odtenphy_lp4_cs_drv_odtofflp4_odte_cklp4_odte_cs_enlp4_odtd_ca_enphy_lp4_dq_vref_when_odtenlp4_dq_vref_when_odtenlp4_ca_vref_when_odtenphy_lp4_dq_vref_when_odtofflp4_dq_vref_when_odtofflp4_ca_vref_when_odtoffddr2_bytes_mapddr3_bytes_mapddr4_bytes_maplp2_bytes_maplp3_bytes_maplp4_bytes_maplp3_dq0_7_maplp2_dq0_7_mapddr4_cs0_dq0_dq15_mapddr4_cs0_dq16_dq31_mapddr4_cs1_dq0_dq15_mapddr4_cs1_dq16_dq31_maplp4x_f1_freq_mhzlp4x_f2_freq_mhzlp4x_f3_freq_mhzlp4x_f4_freq_mhzlp4x_f5_freq_mhzphy_lp4x_dq_drv_when_odten_ohmphy_lp4x_ca_drv_when_odten_ohmphy_lp4x_clk_drv_when_odten_ohmlp4x_dq_drv_when_odten_ohmphy_lp4x_dq_drv_when_odtoff_ohmphy_lp4x_ca_drv_when_odtoff_ohmphy_lp4x_clk_drv_when_odtoff_ohmlp4x_dq_drv_when_odtoff_ohmphy_lp4x_odt_ohmlp4x_odt_ohmlp4x_ca_odt_ohmlp4x_drv_pu_cal_odtenlp4x_drv_pu_cal_odtoffphy_lp4x_drv_pull_dn_en_odtenphy_lp4x_drv_pull_dn_en_odtoffphy_lp4x_odten_freq_mhzlp4x_dq_odten_freq_mhzphy_lp4x_dq_sr_when_odtenphy_lp4x_ca_sr_when_odtenphy_lp4x_clk_sr_when_odtenphy_lp4x_dq_sr_when_odtoffphy_lp4x_ca_sr_when_odtoffphy_lp4x_clk_sr_when_odtofflp4x_ca_odten_freq_mhzphy_lp4x_cs_drv_odtenphy_lp4x_cs_drv_odtofflp4x_odte_cklp4x_odte_cs_enlp4x_odtd_ca_enphy_lp4x_dq_vref_when_odtenlp4x_dq_vref_when_odtenlp4x_ca_vref_when_odtenphy_lp4x_dq_vref_when_odtofflp4x_dq_vref_when_odtofflp4x_ca_vref_when_odtofflp5_f1_freq_mhzlp5_f2_freq_mhzlp5_f3_freq_mhzlp5_f4_freq_mhzlp5_f5_freq_mhzphy_lp5_dq_drv_when_odten_ohmphy_lp5_ca_drv_when_odten_ohmphy_lp5_clk_drv_when_odten_ohmlp5_dq_drv_when_odten_ohmphy_lp5_dq_drv_when_odtoff_ohmphy_lp5_ca_drv_when_odtoff_ohmphy_lp5_clk_drv_when_odtoff_ohmlp5_dq_drv_when_odtoff_ohmphy_lp5_odt_ohmlp5_odt_ohmlp5_ca_odt_ohmlp5_drv_pu_cal_odtenlp5_drv_pu_cal_odtoffphy_lp5_drv_pull_dn_en_odtenphy_lp5_drv_pull_dn_en_odtoffphy_lp5_odten_freq_mhzlp5_dq_odten_freq_mhzphy_lp5_dq_sr_when_odtenphy_lp5_ca_sr_when_odtenphy_lp5_clk_sr_when_odtenphy_lp5_dq_sr_when_odtoffphy_lp5_ca_sr_when_odtoffphy_lp5_clk_sr_when_odtofflp5_ca_odten_freq_mhzlp5_wck_odt_en_freqlp5_wck_odtphy_lp5_cs_drv_odtenphy_lp5_cs_drv_odtofflp5_odte_cklp5_odte_cs_enlp5_odtd_ca_enlp5_nt_odtphy_lp5_dq_vref_when_odtenlp5_dq_vref_when_odtenlp5_ca_vref_when_odtenphy_lp5_dq_vref_when_odtofflp5_dq_vref_when_odtofflp5_ca_vref_when_odtoffch_mask0ch_mask1bank_mask0bank_mask1bank_mask2bank_mask3rank_mask0rank_mask1ddr3_skew_freq_mhzddr3_ca0_skewddr3_ca1_skewddr3_ca2_skewddr3_ca3_skewddr3_ca4_skewddr3_ca5_skewddr3_ca6_skewddr3_ca7_skewddr3_ca8_skewddr3_ca9_skewddr3_ca10_skewddr3_ca11_skewddr3_ca12_skewddr3_ca13_skewddr3_ca14_skewddr3_ca15_skewddr3_ras_skewddr3_cas_skewddr3_ba0_skewddr3_ba1_skewddr3_ba2_skewddr3_we_skewddr3_cke0_skewddr3_cke1_skewddr3_ckn_skewddr3_ckp_skewddr3_odt0_skewddr3_odt1_skewddr3_cs0_skewddr3_cs1_skewddr3_resetn_skewddr4_skew_freq_mhzddr4_ca0_skewddr4_ca1_skewddr4_ca2_skewddr4_ca3_skewddr4_ca4_skewddr4_ca5_skewddr4_ca6_skewddr4_ca7_skewddr4_ca8_skewddr4_ca9_skewddr4_ca10_skewddr4_ca11_skewddr4_ca12_skewddr4_ca13_skewddr4_ca14_skewddr4_ca15_skewddr4_ca16_skewddr4_ca17_skewddr4_ba0_skewddr4_ba1_skewddr4_bg0_skewddr4_bg1_skewddr4_cke0_skewddr4_cke1_skewddr4_ckn_skewddr4_ckp_skewddr4_odt0_skewddr4_odt1_skewddr4_cs0_skewddr4_cs1_skewddr4_resetn_skewddr4_actn_skewlp3_skew_freq_mhzlp3_ca0_skewlp3_ca1_skewlp3_ca2_skewlp3_ca3_skewlp3_ca4_skewlp3_ca5_skewlp3_ca6_skewlp3_ca7_skewlp3_ca8_skewlp3_ca9_skewlp3_cke0_skewlp3_cke1_skewlp3_ckn_skewlp3_ckp_skewlp3_odt0_skewlp3_odt1_skewlp3_odt2_skewlp3_odt3_skewlp3_cs0_skewlp3_cs1_skewlp3_cs2_skewlp3_cs3_skewlp4_skew_freq_mhzlp4_ca0_a_skewlp4_ca1_a_skewlp4_ca2_a_skewlp4_ca3_a_skewlp4_ca4_a_skewlp4_ca5_a_skewlp4_odt0_a_skewlp4_odt1_a_skewlp4_cke0_a_skewlp4_cke1_a_skewlp4_ckn_a_skewlp4_ckp_a_skewlp4_cs0_a_skewlp4_cs1_a_skewlp4_ca0_b_skewlp4_ca1_b_skewlp4_ca2_b_skewlp4_ca3_b_skewlp4_ca4_b_skewlp4_ca5_b_skewlp4_odt0_b_skewlp4_odt1_b_skewlp4_cke0_b_skewlp4_cke1_b_skewlp4_ckn_b_skewlp4_ckp_b_skewlp4_cs0_b_skewlp4_cs1_b_skewlp4_resetn_skewlp5_skew_freq_mhzlp5_ca0_a_skewlp5_ca1_a_skewlp5_ca2_a_skewlp5_ca3_a_skewlp5_ca4_a_skewlp5_ca5_a_skewlp5_ca6_a_skewlp5_ckn_a_skewlp5_ckp_a_skewlp5_cs0_a_skewlp5_cs1_a_skewlp5_ca0_b_skewlp5_ca1_b_skewlp5_ca2_b_skewlp5_ca3_b_skewlp5_ca4_b_skewlp5_ca5_b_skewlp5_ca6_b_skewlp5_ckn_b_skewlp5_ckp_b_skewlp5_cs0_b_skewlp5_cs1_b_skewlp5_resetn_skew; ÿÿÐÐ!ÿÿøà!ÿÿ#ÿÿ¸ù#ÿÿ(j$ÿÿHkÿÿhõÿÿ'ÿÿ¨Ð ÿÿÈ7©ÿÿè¬«ÿÿ¬ÿÿ(/¬ÿÿHUºÿÿhQ¾ÿÿÇÿÿ¨pÇÿÿðzRxP"ÿÿ/D$4¸ÿÿ@FJw?:*3$"\Ð ÿÿtÈ ÿÿ0É"ÿÿqEC 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7phy_ddr3_ca_sr_when_odtofflp2_f2_freq_mhzphy_ddr2_odt_pull_dn_enphy_lp4x_dq_drv_when_odtoff_ohmphy_lp4_cs_drv_odtofflp3_cs2_skewreserved_ddr_0x4_bit24_31lp3_ca_vref_when_odtoffphy_ddr4_dq_vref_when_odtenreserved_global_0x10_bit5_11lp4x_drv_pu_cal_odtenres_space_remap_allch_addr3_ba0_skewch_bphy_ddr3_odt_pull_up_enphy_lp4_drv_pull_dn_en_odtofflp5_ca_odten_freq_mhzphy_ddr2_dq_vref_when_odtoffddr4_ca10_skewddr4reserved_skew_rk3528_0x4_bit12_31long long intddr3_ca_vref_when_odtenreserved_ddr_0x14_bit20_31phy_lp4_clk_drv_when_odtoff_ohmlp3_ca0_skewrk3528_skew_infoddr4_ca12_skewlp4_ca1_a_skewlp4_ca_vref_when_odtofflp5_ca2_b_skewext_temp_reflp5_f5_freq_mhzbank_mask3main.cddr4_ca8_skewlp4_infophy_ddr2_ca_sr_when_odtoff_IO_write_endddr4_dq_mapddr4_cke0_skewddr3_ca12_skewlp2_indexddr3_f2_freq_mhzphy_lp4x_cs_drv_odtenuboot_log_enlp4_ca_vref_when_odtenlp5_cs1_b_skewlp3_f4_freq_mhzlp4_drv_pu_cal_odtoffcs_drv_ca_odt_inforeserved_lp4_5_0x4_bit24_31skew_sub_verlp4x_f3_freq_mhzbin_skew_offsetddr3_cke0_skewphy_lp5_dq_sr_when_odtenphy_ddr2_odten_freq_mhzreserved_ddr_0x20_bit24_31sdram_head_info_v5lp4_ca_odt_ohmbase_info_tag_sizehash_infolp5_ca1_b_skewlp4_skew_freq_mhz_IO_buf_basereserved_global_0x14_bit9_31ddr2_ca_vref_when_odtoffddr3_resetn_skewinfo_from_txtddr4_ca1_skewddr4_ca4_skewlp3_odt2_skewsizeof_sdram_head_infophy_lp4x_clk_sr_when_odtofflp4x_f2_freq_mhzreserved_skew_rk3528_0x0_bit8_31write_in_bin_data_v2__pad5phy_ddr4_dq_vref_when_odtoffphy_lp5_dq_sr_when_odtoffphy_ddr2_ca_sr_when_odtenlink_ecc_enddr4_cs0_dq0_dq15_mapddr4_f4_freq_mhzddr4_freqphy_lp2_clk_drv_when_odten_ohmch_mask1lp4x_ca_vref_when_odtenphy_ddr3_clk_sr_when_odtofflp3_ca8_skewphy_lp5_clk_sr_when_odtoffgen_info_from_binphy_lp2_odt_pull_dn_en_flagsreserved_ddr_0x28_bit30_31ddr4_bg0_skewphy_ddr2_dq_vref_when_odtenddr2_f3_freq_mhzlp4_indexphy_lp4x_ca_sr_when_odten_modebin_data_2_infolpddr4x_infophy_lp5_odt_ohmglobal_infotxt_infophy_lp4_dq_drv_when_odtoff_ohmlp4_f2_freq_mhzddr3_ca9_skewddr_freq0_1ddr4_odt0_skewlp4x_indexlp3_ca1_skewlp3_dq0_7_maplp4_bytes_mapbank_mask0bank_mask1bank_mask2phy_lp4x_clk_drv_when_odten_ohmbank_maskpskipddr3_freqddr4_ca_vref_when_odtoffphy_lp4x_dq_sr_when_odtenparam_lenphy_lp4x_drv_pull_dn_en_odtofflp2_ca_vref_when_odtenddr4_resetn_skewlp5_indexlp2_dq0_7_maplp4_ca0_b_skewwr_vref_scan_enlp4_resetn_skewlp3_bytes_maplp5_ca1_a_skewddr3_f5_freq_mhzddr4_cs0_dq16_dq31_mapphy_lp2_dq_vref_when_odtoffsr_idlelp5_ca0_a_skewddr3_ca2_skewca_odten_freqp_v5ddr2_indexoptoptphy_ddr3_clk_drv_when_odten_ohmch_mask0phy_lp2_ca_sr_when_odtentext_infophy_lp4_ca_drv_when_odten_ohmlong long unsigned intphy_lp4_dq_sr_when_odtofflp5_f4_freq_mhzphy_ddr4_clk_drv_when_odtoff_ohmlp4x_ca_odt_ohmuart_baudrateindex_sizelengthddr3_ca8_skewphy_ddr3_dq_vref_when_odtoff__off_tphy_lp2_dq_drv_when_odten_ohmrk322x_enddr4_ca16_skewddr3_f1_freq_mhzlp3_ca2_skewbin_data_readoutphy_ddr4_odten_freq_mhzeye_2d_scan_enddr3_ca_skewlp3_f3_freq_mhzlp4x_ca_odten_freq_mhzlp4_odt1_b_skew_freeres_bufphy_lp5_drv_pull_dn_en_odtoffphy_lp3_odt_pull_up_enphy_lp4_clk_drv_when_odten_ohmphy_ddr3_dq_drv_when_odten_ohmphy_lp5_dq_vref_when_odtenlp5_wck_odt_en_freqphy_ddr4_dq_sr_when_odtoffphy_ddr4_dq_sr_when_odtenchannel_maskopterrddr3_indexbin_offsetlp4_ckn_b_skewlp4_ca4_a_skewphy_lp3_dq_sr_when_odtoffddr3_odt0_skewddr3_ca1_skewddr3_cs0_skewlp3_odt3_skewhash_indexrk3528_skewpageclose_IO_backup_base_shortbufreserved_ddr_0x1c_bit24_31closefilegenphy_ddr2_dq_drv_when_odtoff_ohmreserved_ddr_0x8_bit24_31lp4_odt0_b_skewphy_lp3_ca_sr_when_odtoffrk3528_ca_skewgloballp4_cke1_b_skew__off64_tddr4_f3_freq_mhzlp4_cs1_a_skewreserved_lp5_0x28_bit19_23phy_ddr2_odt_ohmphy_ddr3_dq_sr_when_odtofflp4_f5_freq_mhzphy_lp3_clk_drv_when_odtoff_ohmlp4_freqphy_lp2_odten_freq_mhzlp4_odt1_a_skewddr4_indexddr4_cs1_skewlp4_odtd_ca_enlp4_cs0_b_skewddr2_f2_freq_mhz_IO_buf_endresetphy_lp3_dq_drv_when_odtoff_ohmreserved_lp4_0x24_bit12_31reserved_ddr_0x18_bit24_31lp5_ca5_a_skewphy_lp2_ca_sr_when_odtoffddr4_bytes_mapreserved_lp4_5_0x30_bit30_31lp3_ca4_skewphy_lp4x_dq_vref_when_odtenbyte_mapreserved_lp4_5_0x8_bit24_31stderrlp4_f1_freq_mhzshort intlp5_drv_pu_cal_odtofflp5_ckp_a_skewddr3_we_skewddr3_ckp_skewddr3_bytes_mapphy_lp5_ca_sr_when_odtenddr5_indexatf_log_enlp3_freq_vtable_offsetphy_lp4x_ca_drv_when_odtoff_ohmphy_lp4_clk_sr_when_odtofflp5_ca4_a_skewddr2_bytes_mapddr3_f4_freq_mhzddr3_ca5_skewphy_lp4_dq_vref_when_odtenlp3_ckn_skewphy_lp3_dq_vref_when_odtenphy_ddr4_odt_pull_dn_enddr4_cs1_dq16_dq31_maplp3_cs1_skewphy_lp4x_clk_sr_when_odtenlp4_ca0_a_skewsr_pd_infoderate_enlp5_f3_freq_mhzwrite_inclosefilebinssmod_downspreadphy_lp3_dq_vref_when_odtoffphy_lp4_dq_drv_when_odten_ohm_IO_read_endphy_ddr4_dq_drv_when_odtoff_ohmin_infolp3_f2_freq_mhzlp5_cs0_b_skewlp4x_f1_freq_mhzddr4_ca7_skewlpddr5_infoddr3_ca11_skewlp4x_odte_ck_filenophy_lp4x_odt_ohmphy_ddr3_clk_drv_when_odtoff_ohmddr3_ca4_skewlp5_ca0_b_skewphy_lp4_ca_drv_when_odtoff_ohmoptargreservedpatternddr4_ba1_skewlp3_cs0_skewmax_itemlp4_odte_cs_enphy_lp4x_ca_sr_when_odtofflp4x_odtd_ca_enphy_ddr3_dq_sr_when_odtenphy_lp5_dq_drv_when_odtoff_ohmshort unsigned intstdoutsdram_head_info_v2lp3_skew_freq_mhzddr4_ca_vref_when_odtenlp2_f5_freq_mhzphy_lp4_dq_sr_when_odtenphy_lp3_ca_drv_when_odten_ohm_IO_write_ptrddr4_ca0_skewlp5_dq_odten_freq_mhzphy_lp4_odten_freq_mhzlp3_odt1_skewreserved_global_0xc_bit31ddr4_f2_freq_mhzphy_lp5_dq_drv_when_odten_ohmlp4_f4_freq_mhzcs_lch_infophy_ddr4_ca_drv_when_odten_ohmfind_param_numphy_lp2_odt_ohmddr3_cs1_skewlp4_drv_pu_cal_odtenp_v2lpddr4_infofirst_init_dram_typeoptee_log_enlp5_ca_vref_when_odtenhashddr2_f1_freq_mhzddr_infolp5_ca_skewlp5_cs1_a_skewpstore_buf_sizephy_ddr2_dq_drv_when_odten_ohmlp5_wck_odtphy_lp2_odt_pull_up_enlp5_ca_odt_ohmlp3_ca7_skewlp4_ca5_b_skewlp4_ca_skewphy_ddr2_ca_drv_when_odtoff_ohmphy_lp5_cs_drv_odtoffphy_ddr3_odt_ohmlp3_cke1_skewd3_ca_mapp_cashiftlp3_ca_maprk3528_dram.crk3528_ca_skew_read_outd4_ca_mapddrbin_skewrk3528_mdf_ca_skewparameters.c8X| ÐXl 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