/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* include/linux/platform_data/pxa_sdhci.h
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*
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* Copyright 2010 Marvell
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* Zhangfei Gao <zhangfei.gao@marvell.com>
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*
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* PXA Platform - SDHCI platform data definitions
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*/
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#ifndef _PXA_SDHCI_H_
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#define _PXA_SDHCI_H_
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/* pxa specific flag */
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/* Require clock free running */
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#define PXA_FLAG_ENABLE_CLOCK_GATING (1<<0)
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/* card always wired to host, like on-chip emmc */
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#define PXA_FLAG_CARD_PERMANENT (1<<1)
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/* Board design supports 8-bit data on SD/SDIO BUS */
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#define PXA_FLAG_SD_8_BIT_CAPABLE_SLOT (1<<2)
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/*
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* struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
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* @flags: flags for platform requirement
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* @clk_delay_cycles:
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* mmp2: each step is roughly 100ps, 5bits width
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* pxa910: each step is 1ns, 4bits width
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* @clk_delay_sel: select clk_delay, used on pxa910
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* 0: choose feedback clk
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* 1: choose feedback clk + delay value
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* 2: choose internal clk
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* @clk_delay_enable: enable clk_delay or not, used on pxa910
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* @max_speed: the maximum speed supported
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* @host_caps: Standard MMC host capabilities bit field.
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* @quirks: quirks of platfrom
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* @quirks2: quirks2 of platfrom
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* @pm_caps: pm_caps of platfrom
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*/
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struct sdhci_pxa_platdata {
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unsigned int flags;
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unsigned int clk_delay_cycles;
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unsigned int clk_delay_sel;
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bool clk_delay_enable;
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unsigned int max_speed;
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u32 host_caps;
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u32 host_caps2;
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unsigned int quirks;
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unsigned int quirks2;
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unsigned int pm_caps;
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};
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#endif /* _PXA_SDHCI_H_ */
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