/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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// Copyright (c) 2017 Synopsys, Inc. and/or its affiliates.
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// stmmac Support for 5.xx Ethernet QoS cores
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#ifndef __DWMAC5_H__
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#define __DWMAC5_H__
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#define MAC_DPP_FSM_INT_STATUS 0x00000140
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#define MAC_AXI_SLV_DPE_ADDR_STATUS 0x00000144
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#define MAC_FSM_CONTROL 0x00000148
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#define PRTYEN BIT(1)
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#define TMOUTEN BIT(0)
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#define MAC_FPE_CTRL_STS 0x00000234
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#define EFPE BIT(0)
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#define MAC_PPS_CONTROL 0x00000b70
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#define PPS_MAXIDX(x) ((((x) + 1) * 8) - 1)
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#define PPS_MINIDX(x) ((x) * 8)
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#define PPSx_MASK(x) GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x))
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#define MCGRENx(x) BIT(PPS_MAXIDX(x))
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#define TRGTMODSELx(x, val) \
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GENMASK(PPS_MAXIDX(x) - 1, PPS_MAXIDX(x) - 2) & \
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((val) << (PPS_MAXIDX(x) - 2))
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#define PPSCMDx(x, val) \
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GENMASK(PPS_MINIDX(x) + 3, PPS_MINIDX(x)) & \
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((val) << PPS_MINIDX(x))
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#define PPSEN0 BIT(4)
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#define MAC_PPSx_TARGET_TIME_SEC(x) (0x00000b80 + ((x) * 0x10))
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#define MAC_PPSx_TARGET_TIME_NSEC(x) (0x00000b84 + ((x) * 0x10))
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#define TRGTBUSY0 BIT(31)
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#define TTSL0 GENMASK(30, 0)
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#define MAC_PPSx_INTERVAL(x) (0x00000b88 + ((x) * 0x10))
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#define MAC_PPSx_WIDTH(x) (0x00000b8c + ((x) * 0x10))
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#define MTL_EST_CONTROL 0x00000c50
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#define PTOV GENMASK(31, 24)
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#define PTOV_SHIFT 24
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#define SSWL BIT(1)
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#define EEST BIT(0)
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#define MTL_EST_GCL_CONTROL 0x00000c80
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#define BTR_LOW 0x0
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#define BTR_HIGH 0x1
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#define CTR_LOW 0x2
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#define CTR_HIGH 0x3
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#define TER 0x4
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#define LLR 0x5
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#define ADDR_SHIFT 8
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#define GCRR BIT(2)
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#define SRWO BIT(0)
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#define MTL_EST_GCL_DATA 0x00000c84
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#define MTL_RXP_CONTROL_STATUS 0x00000ca0
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#define RXPI BIT(31)
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#define NPE GENMASK(23, 16)
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#define NVE GENMASK(7, 0)
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#define MTL_RXP_IACC_CTRL_STATUS 0x00000cb0
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#define STARTBUSY BIT(31)
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#define RXPEIEC GENMASK(22, 21)
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#define RXPEIEE BIT(20)
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#define WRRDN BIT(16)
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#define ADDR GENMASK(15, 0)
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#define MTL_RXP_IACC_DATA 0x00000cb4
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#define MTL_ECC_CONTROL 0x00000cc0
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#define TSOEE BIT(4)
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#define MRXPEE BIT(3)
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#define MESTEE BIT(2)
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#define MRXEE BIT(1)
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#define MTXEE BIT(0)
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#define MTL_SAFETY_INT_STATUS 0x00000cc4
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#define MCSIS BIT(31)
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#define MEUIS BIT(1)
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#define MECIS BIT(0)
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#define MTL_ECC_INT_ENABLE 0x00000cc8
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#define RPCEIE BIT(12)
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#define ECEIE BIT(8)
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#define RXCEIE BIT(4)
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#define TXCEIE BIT(0)
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#define MTL_ECC_INT_STATUS 0x00000ccc
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#define MTL_DPP_CONTROL 0x00000ce0
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#define EPSI BIT(2)
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#define OPE BIT(1)
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#define EDPP BIT(0)
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#define DMA_SAFETY_INT_STATUS 0x00001080
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#define MSUIS BIT(29)
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#define MSCIS BIT(28)
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#define DEUIS BIT(1)
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#define DECIS BIT(0)
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#define DMA_ECC_INT_ENABLE 0x00001084
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#define TCEIE BIT(0)
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#define DMA_ECC_INT_STATUS 0x00001088
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/* EQoS version 5.xx VLAN Tag Filter Fail Packets Queuing */
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#define GMAC_RXQ_CTRL4 0x00000094
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#define GMAC_RXQCTRL_VFFQ_MASK GENMASK(19, 17)
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#define GMAC_RXQCTRL_VFFQ_SHIFT 17
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#define GMAC_RXQCTRL_VFFQE BIT(16)
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int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp);
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int dwmac5_safety_feat_irq_status(struct net_device *ndev,
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void __iomem *ioaddr, unsigned int asp,
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struct stmmac_safety_stats *stats);
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int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats,
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int index, unsigned long *count, const char **desc);
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int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries,
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unsigned int count);
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int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,
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struct stmmac_pps_cfg *cfg, bool enable,
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u32 sub_second_inc, u32 systime_flags);
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int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
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unsigned int ptp_rate);
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void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
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bool enable);
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#endif /* __DWMAC5_H__ */
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