// SPDX-License-Identifier: GPL-2.0-only
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/*******************************************************************************
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This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
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developing this code.
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This only implements the mac core functions for this chip.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/crc32.h>
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#include <linux/slab.h>
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#include <linux/ethtool.h>
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#include <net/dsa.h>
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#include <asm/io.h>
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#include "stmmac.h"
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#include "stmmac_pcs.h"
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#include "dwmac1000.h"
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static void dwmac1000_core_init(struct mac_device_info *hw,
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struct net_device *dev)
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{
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struct stmmac_priv *priv = netdev_priv(dev);
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + GMAC_CONTROL);
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int mtu = dev->mtu;
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/* Configure GMAC core */
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value |= GMAC_CORE_INIT;
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/* Clear ACS bit because Ethernet switch tagging formats such as
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* Broadcom tags can look like invalid LLC/SNAP packets and cause the
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* hardware to truncate packets on reception.
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*/
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if (netdev_uses_dsa(dev) || !priv->plat->enh_desc)
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value &= ~GMAC_CONTROL_ACS;
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if (mtu > 1500)
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value |= GMAC_CONTROL_2K;
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if (mtu > 2000)
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value |= GMAC_CONTROL_JE;
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if (hw->ps) {
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value |= GMAC_CONTROL_TE;
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value &= ~hw->link.speed_mask;
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switch (hw->ps) {
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case SPEED_1000:
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value |= hw->link.speed1000;
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break;
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case SPEED_100:
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value |= hw->link.speed100;
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break;
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case SPEED_10:
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value |= hw->link.speed10;
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break;
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}
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}
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writel(value, ioaddr + GMAC_CONTROL);
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/* Mask GMAC interrupts */
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value = GMAC_INT_DEFAULT_MASK;
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if (hw->pcs)
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value &= ~GMAC_INT_DISABLE_PCS;
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writel(value, ioaddr + GMAC_INT_MASK);
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#ifdef STMMAC_VLAN_TAG_USED
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/* Tag detection without filtering */
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writel(0x0, ioaddr + GMAC_VLAN_TAG);
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#endif
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}
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static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + GMAC_CONTROL);
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if (hw->rx_csum)
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value |= GMAC_CONTROL_IPC;
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else
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value &= ~GMAC_CONTROL_IPC;
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writel(value, ioaddr + GMAC_CONTROL);
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value = readl(ioaddr + GMAC_CONTROL);
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return !!(value & GMAC_CONTROL_IPC);
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}
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static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
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{
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void __iomem *ioaddr = hw->pcsr;
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int i;
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for (i = 0; i < 55; i++)
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reg_space[i] = readl(ioaddr + i * 4);
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}
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static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
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unsigned char *addr,
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unsigned int reg_n)
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{
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void __iomem *ioaddr = hw->pcsr;
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stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
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unsigned char *addr,
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unsigned int reg_n)
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{
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void __iomem *ioaddr = hw->pcsr;
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stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
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int mcbitslog2)
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{
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int numhashregs, regs;
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switch (mcbitslog2) {
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case 6:
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writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
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writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
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return;
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case 7:
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numhashregs = 4;
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break;
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case 8:
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numhashregs = 8;
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break;
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default:
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pr_debug("STMMAC: err in setting multicast filter\n");
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return;
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}
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for (regs = 0; regs < numhashregs; regs++)
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writel(mcfilterbits[regs],
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ioaddr + GMAC_EXTHASH_BASE + regs * 4);
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}
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static void dwmac1000_set_filter(struct mac_device_info *hw,
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struct net_device *dev)
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{
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void __iomem *ioaddr = (void __iomem *)dev->base_addr;
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unsigned int value = 0;
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unsigned int perfect_addr_number = hw->unicast_filter_entries;
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u32 mc_filter[8];
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int mcbitslog2 = hw->mcast_bits_log2;
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pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
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netdev_mc_count(dev), netdev_uc_count(dev));
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memset(mc_filter, 0, sizeof(mc_filter));
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if (dev->flags & IFF_PROMISC) {
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value = GMAC_FRAME_FILTER_PR | GMAC_FRAME_FILTER_PCF;
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} else if (dev->flags & IFF_ALLMULTI) {
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value = GMAC_FRAME_FILTER_PM; /* pass all multi */
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} else if (!netdev_mc_empty(dev) && (mcbitslog2 == 0)) {
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/* Fall back to all multicast if we've no filter */
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value = GMAC_FRAME_FILTER_PM;
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} else if (!netdev_mc_empty(dev)) {
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struct netdev_hw_addr *ha;
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/* Hash filter for multicast */
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value = GMAC_FRAME_FILTER_HMC;
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netdev_for_each_mc_addr(ha, dev) {
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/* The upper n bits of the calculated CRC are used to
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* index the contents of the hash table. The number of
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* bits used depends on the hardware configuration
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* selected at core configuration time.
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*/
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int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
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ETH_ALEN)) >>
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(32 - mcbitslog2);
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/* The most significant bit determines the register to
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* use (H/L) while the other 5 bits determine the bit
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* within the register.
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*/
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mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
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}
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}
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value |= GMAC_FRAME_FILTER_HPF;
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dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
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/* Handle multiple unicast addresses (perfect filtering) */
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if (netdev_uc_count(dev) > perfect_addr_number)
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/* Switch to promiscuous mode if more than unicast
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* addresses are requested than supported by hardware.
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*/
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value |= GMAC_FRAME_FILTER_PR;
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else {
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int reg = 1;
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struct netdev_hw_addr *ha;
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netdev_for_each_uc_addr(ha, dev) {
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stmmac_set_mac_addr(ioaddr, ha->addr,
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GMAC_ADDR_HIGH(reg),
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GMAC_ADDR_LOW(reg));
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reg++;
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}
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while (reg < perfect_addr_number) {
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writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
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writel(0, ioaddr + GMAC_ADDR_LOW(reg));
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reg++;
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}
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}
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#ifdef FRAME_FILTER_DEBUG
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/* Enable Receive all mode (to debug filtering_fail errors) */
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value |= GMAC_FRAME_FILTER_RA;
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#endif
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writel(value, ioaddr + GMAC_FRAME_FILTER);
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}
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static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
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unsigned int fc, unsigned int pause_time,
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u32 tx_cnt)
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{
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void __iomem *ioaddr = hw->pcsr;
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/* Set flow such that DZPQ in Mac Register 6 is 0,
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* and unicast pause detect is enabled.
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*/
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unsigned int flow = GMAC_FLOW_CTRL_UP;
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pr_debug("GMAC Flow-Control:\n");
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if (fc & FLOW_RX) {
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pr_debug("\tReceive Flow-Control ON\n");
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flow |= GMAC_FLOW_CTRL_RFE;
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}
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if (fc & FLOW_TX) {
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pr_debug("\tTransmit Flow-Control ON\n");
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flow |= GMAC_FLOW_CTRL_TFE;
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}
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if (duplex) {
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pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
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flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
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}
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writel(flow, ioaddr + GMAC_FLOW_CTRL);
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}
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static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
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{
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void __iomem *ioaddr = hw->pcsr;
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unsigned int pmt = 0;
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if (mode & WAKE_MAGIC) {
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pr_debug("GMAC: WOL Magic frame\n");
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pmt |= power_down | magic_pkt_en;
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}
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if (mode & WAKE_UCAST) {
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pr_debug("GMAC: WOL on global unicast\n");
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pmt |= power_down | global_unicast | wake_up_frame_en;
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}
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writel(pmt, ioaddr + GMAC_PMT);
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}
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/* RGMII or SMII interface */
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static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
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{
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u32 status;
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status = readl(ioaddr + GMAC_RGSMIIIS);
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x->irq_rgmii_n++;
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/* Check the link status */
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if (status & GMAC_RGSMIIIS_LNKSTS) {
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int speed_value;
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x->pcs_link = 1;
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speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
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GMAC_RGSMIIIS_SPEED_SHIFT);
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if (speed_value == GMAC_RGSMIIIS_SPEED_125)
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x->pcs_speed = SPEED_1000;
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else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
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x->pcs_speed = SPEED_100;
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else
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x->pcs_speed = SPEED_10;
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x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
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pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
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x->pcs_duplex ? "Full" : "Half");
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} else {
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x->pcs_link = 0;
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pr_info("Link is Down\n");
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}
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}
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static int dwmac1000_irq_status(struct mac_device_info *hw,
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struct stmmac_extra_stats *x)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
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u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
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int ret = 0;
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/* Discard masked bits */
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intr_status &= ~intr_mask;
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/* Not used events (e.g. MMC interrupts) are not handled. */
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if ((intr_status & GMAC_INT_STATUS_MMCTIS))
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x->mmc_tx_irq_n++;
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if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
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x->mmc_rx_irq_n++;
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if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
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x->mmc_rx_csum_offload_irq_n++;
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if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
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/* clear the PMT bits 5 and 6 by reading the PMT status reg */
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readl(ioaddr + GMAC_PMT);
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x->irq_receive_pmt_irq_n++;
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}
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/* MAC tx/rx EEE LPI entry/exit interrupts */
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if (intr_status & GMAC_INT_STATUS_LPIIS) {
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/* Clean LPI interrupt by reading the Reg 12 */
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ret = readl(ioaddr + LPI_CTRL_STATUS);
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if (ret & LPI_CTRL_STATUS_TLPIEN)
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x->irq_tx_path_in_lpi_mode_n++;
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if (ret & LPI_CTRL_STATUS_TLPIEX)
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x->irq_tx_path_exit_lpi_mode_n++;
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if (ret & LPI_CTRL_STATUS_RLPIEN)
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x->irq_rx_path_in_lpi_mode_n++;
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if (ret & LPI_CTRL_STATUS_RLPIEX)
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x->irq_rx_path_exit_lpi_mode_n++;
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}
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dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
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if (intr_status & PCS_RGSMIIIS_IRQ)
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dwmac1000_rgsmii(ioaddr, x);
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return ret;
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}
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static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
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bool en_tx_lpi_clockgating)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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/*TODO - en_tx_lpi_clockgating treatment */
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/* Enable the link status receive on RGMII, SGMII ore SMII
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* receive path and instruct the transmit to enter in LPI
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* state.
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*/
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value = readl(ioaddr + LPI_CTRL_STATUS);
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value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
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writel(value, ioaddr + LPI_CTRL_STATUS);
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}
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static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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value = readl(ioaddr + LPI_CTRL_STATUS);
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value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
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writel(value, ioaddr + LPI_CTRL_STATUS);
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}
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static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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value = readl(ioaddr + LPI_CTRL_STATUS);
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if (link)
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value |= LPI_CTRL_STATUS_PLS;
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else
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value &= ~LPI_CTRL_STATUS_PLS;
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writel(value, ioaddr + LPI_CTRL_STATUS);
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}
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static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
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{
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void __iomem *ioaddr = hw->pcsr;
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int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
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/* Program the timers in the LPI timer control register:
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* LS: minimum time (ms) for which the link
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* status from PHY should be ok before transmitting
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* the LPI pattern.
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* TW: minimum time (us) for which the core waits
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* after it has stopped transmitting the LPI pattern.
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*/
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writel(value, ioaddr + LPI_TIMER_CTRL);
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}
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static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
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bool loopback)
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{
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dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
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}
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static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
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{
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dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
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}
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static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
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{
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dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
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}
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static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
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u32 rx_queues, u32 tx_queues)
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{
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u32 value = readl(ioaddr + GMAC_DEBUG);
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if (value & GMAC_DEBUG_TXSTSFSTS)
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x->mtl_tx_status_fifo_full++;
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if (value & GMAC_DEBUG_TXFSTS)
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x->mtl_tx_fifo_not_empty++;
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if (value & GMAC_DEBUG_TWCSTS)
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x->mmtl_fifo_ctrl++;
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if (value & GMAC_DEBUG_TRCSTS_MASK) {
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u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
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>> GMAC_DEBUG_TRCSTS_SHIFT;
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if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
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x->mtl_tx_fifo_read_ctrl_write++;
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else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
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x->mtl_tx_fifo_read_ctrl_wait++;
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else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
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x->mtl_tx_fifo_read_ctrl_read++;
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else
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x->mtl_tx_fifo_read_ctrl_idle++;
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}
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if (value & GMAC_DEBUG_TXPAUSED)
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x->mac_tx_in_pause++;
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if (value & GMAC_DEBUG_TFCSTS_MASK) {
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u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
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>> GMAC_DEBUG_TFCSTS_SHIFT;
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if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
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x->mac_tx_frame_ctrl_xfer++;
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else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
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x->mac_tx_frame_ctrl_pause++;
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else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
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x->mac_tx_frame_ctrl_wait++;
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else
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x->mac_tx_frame_ctrl_idle++;
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}
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if (value & GMAC_DEBUG_TPESTS)
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x->mac_gmii_tx_proto_engine++;
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if (value & GMAC_DEBUG_RXFSTS_MASK) {
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u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
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>> GMAC_DEBUG_RRCSTS_SHIFT;
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if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
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x->mtl_rx_fifo_fill_level_full++;
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else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
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x->mtl_rx_fifo_fill_above_thresh++;
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else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
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x->mtl_rx_fifo_fill_below_thresh++;
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else
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x->mtl_rx_fifo_fill_level_empty++;
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}
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if (value & GMAC_DEBUG_RRCSTS_MASK) {
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u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
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GMAC_DEBUG_RRCSTS_SHIFT;
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if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
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x->mtl_rx_fifo_read_ctrl_flush++;
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else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
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x->mtl_rx_fifo_read_ctrl_read_data++;
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else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
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x->mtl_rx_fifo_read_ctrl_status++;
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else
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x->mtl_rx_fifo_read_ctrl_idle++;
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}
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if (value & GMAC_DEBUG_RWCSTS)
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x->mtl_rx_fifo_ctrl_active++;
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if (value & GMAC_DEBUG_RFCFCSTS_MASK)
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x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
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>> GMAC_DEBUG_RFCFCSTS_SHIFT;
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if (value & GMAC_DEBUG_RPESTS)
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x->mac_gmii_rx_proto_engine++;
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}
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static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable)
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{
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u32 value = readl(ioaddr + GMAC_CONTROL);
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if (enable)
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value |= GMAC_CONTROL_LM;
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else
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value &= ~GMAC_CONTROL_LM;
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writel(value, ioaddr + GMAC_CONTROL);
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}
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const struct stmmac_ops dwmac1000_ops = {
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.core_init = dwmac1000_core_init,
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.set_mac = stmmac_set_mac,
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.rx_ipc = dwmac1000_rx_ipc_enable,
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.dump_regs = dwmac1000_dump_regs,
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.host_irq_status = dwmac1000_irq_status,
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.set_filter = dwmac1000_set_filter,
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.flow_ctrl = dwmac1000_flow_ctrl,
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.pmt = dwmac1000_pmt,
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.set_umac_addr = dwmac1000_set_umac_addr,
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.get_umac_addr = dwmac1000_get_umac_addr,
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.set_eee_mode = dwmac1000_set_eee_mode,
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.reset_eee_mode = dwmac1000_reset_eee_mode,
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.set_eee_timer = dwmac1000_set_eee_timer,
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.set_eee_pls = dwmac1000_set_eee_pls,
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.debug = dwmac1000_debug,
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.pcs_ctrl_ane = dwmac1000_ctrl_ane,
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.pcs_rane = dwmac1000_rane,
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.pcs_get_adv_lp = dwmac1000_get_adv_lp,
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.set_mac_loopback = dwmac1000_set_mac_loopback,
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};
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int dwmac1000_setup(struct stmmac_priv *priv)
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{
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struct mac_device_info *mac = priv->hw;
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dev_info(priv->device, "\tDWMAC1000\n");
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priv->dev->priv_flags |= IFF_UNICAST_FLT;
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mac->pcsr = priv->ioaddr;
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mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
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mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
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mac->mcast_bits_log2 = 0;
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if (mac->multicast_filter_bins)
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mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
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mac->link.duplex = GMAC_CONTROL_DM;
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mac->link.speed10 = GMAC_CONTROL_PS;
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mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
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mac->link.speed1000 = 0;
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mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
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mac->mii.addr = GMAC_MII_ADDR;
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mac->mii.data = GMAC_MII_DATA;
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mac->mii.addr_shift = 11;
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mac->mii.addr_mask = 0x0000F800;
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mac->mii.reg_shift = 6;
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mac->mii.reg_mask = 0x000007C0;
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mac->mii.clk_csr_shift = 2;
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mac->mii.clk_csr_mask = GENMASK(5, 2);
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return 0;
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}
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