// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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*
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* Author: Guochun Huang <hero.huang@rock-chips.com>
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*/
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#include <asm/unaligned.h>
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#include <dt-bindings/mfd/rockchip-serdes.h>
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#include "rkx110_reg.h"
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#include "rkx110_x120.h"
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#include "rkx110_dsi_rx.h"
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#include "serdes_combphy.h"
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#define DSI_RX_MIPI_IDX_CTRL0(x) (0x0100 + x * 8)
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#define SW_COMMAND_MODE_EN BIT(26)
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#define SW_DT(x) UPDATE(x, 15, 10)
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#define SW_VC(x) UPDATE(x, 9, 8)
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#define SW_CAP_EN BIT(0)
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#define DSI_RX_MIPI_IDX_CTRL1(x) (0X0104 + x * 8)
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#define SW_HEIGHT(x) UPDATE(x, 29, 16)
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#define SW_WIDTH(x) UPDATE(x, 13, 0)
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#define DSI_RX_MIPI_INTEN 0x0174
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#define DSI_RX_MIPI_INTSTAT 0x0178
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#define DSI_RX_MIPI_SIZE_NUM(x) (0x01c0 + x * 4)
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enum {
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VSYNC_START = 0x01,
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VSYNC_END = 0x11,
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HSYNC_START = 0x21,
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HSYNC_END = 0x31,
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};
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static inline int dsi_rx_write(struct rk_serdes *ser, u32 reg, u32 val)
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{
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struct i2c_client *client = ser->chip[DEVICE_LOCAL].client;
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return ser->i2c_write_reg(client, reg, val);
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}
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static inline int dsi_rx_read(struct rk_serdes *ser, u32 reg, u32 *val)
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{
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struct i2c_client *client = ser->chip[DEVICE_LOCAL].client;
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return ser->i2c_read_reg(client, reg, val);
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}
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static inline int dsi_rx_update_bits(struct rk_serdes *ser,
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u32 reg, u32 mask, u32 val)
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{
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struct i2c_client *client = ser->chip[DEVICE_LOCAL].client;
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return ser->i2c_update_bits(client, reg, mask, val);
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}
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void rkx110_dsi_rx_enable(struct rk_serdes *ser, struct rk_serdes_route *route, int id)
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{
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struct rkx110_dsi_rx *dsi = &ser->dsi_rx;
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const struct videomode *vm = &route->vm;
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unsigned long pixelclock;
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u32 hactive, vactive;
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u64 rate;
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u32 val = 0;
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u32 csi_base, dsirx_base;
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switch (route->frame_mode) {
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case SERDES_SP_PIXEL_INTERLEAVED:
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fallthrough;
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case SERDES_SP_LEFT_RIGHT_SPLIT:
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pixelclock = vm->pixelclock * 2;
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hactive = vm->hactive * 2;
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vactive = vm->vactive;
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break;
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case SERDES_SP_LINE_INTERLEAVED:
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pixelclock = vm->pixelclock * 2;
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vactive = vm->vactive * 2;
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hactive = vm->hactive;
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break;
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case SERDES_FRAME_NORMAL_MODE:
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fallthrough;
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default:
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pixelclock = vm->pixelclock;
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hactive = vm->hactive;
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vactive = vm->vactive;
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break;
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}
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rate = DIV_ROUND_CLOSEST_ULL(pixelclock, dsi->lanes);
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rkx110_combrxphy_set_mode(ser, COMBRX_PHY_MODE_VIDEO_MIPI);
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rkx110_combrxphy_set_rate(ser, rate * MSEC_PER_SEC);
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rkx110_combrxphy_power_on(ser, id ? COMBPHY_1 : COMBPHY_0);
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csi_base = id ? RKX110_CSI2HOST1_BASE : RKX110_CSI2HOST0_BASE;
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dsirx_base = id ? RKX110_DSI_RX1_BASE : RKX110_DSI_RX0_BASE;
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dsi_rx_write(ser, csi_base + CSI2HOST_N_LANES, dsi->lanes - 1);
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dsi_rx_write(ser, csi_base + CSI2HOST_RESETN, 0);
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val |= SW_DSI_EN | SW_DATETYPE_FE(VSYNC_END) | SW_DATETYPE_FS(VSYNC_START);
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dsi_rx_update_bits(ser, csi_base + CSI2HOST_CONTROL,
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SW_DATETYPE_FE_MASK |
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SW_DATETYPE_FS_MASK |
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SW_DSI_EN, val);
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dsi_rx_write(ser, csi_base + CSI2HOST_RESETN, 1);
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val = SW_CAP_EN | SW_VC(0);
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/*
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* video mode only support rgb888(0x3e), command mode
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* only support DCS Long Write(0x39)
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*/
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val |= (dsi->mode_flags & SERDES_MIPI_DSI_MODE_VIDEO) ?
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(0 | SW_DT(0x3e)) : (SW_COMMAND_MODE_EN | SW_DT(0x39));
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dsi_rx_write(ser, dsirx_base + DSI_RX_MIPI_IDX_CTRL0(0), val);
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dsi_rx_write(ser, dsirx_base + DSI_RX_MIPI_IDX_CTRL1(0),
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SW_HEIGHT(vactive) | SW_WIDTH(hactive));
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}
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void rkx110_dsi_rx_disable(struct rk_serdes *ser, struct rk_serdes_route *route, int id)
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{
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rkx110_combrxphy_power_off(ser, id ? COMBPHY_1 : COMBPHY_0);
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}
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