MediaTek MT7621 PCIe controller
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Required properties:
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- compatible: "mediatek,mt7621-pci"
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- device_type: Must be "pci"
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- reg: Base addresses and lengths of the PCIe subsys and root ports.
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- bus-range: Range of bus numbers associated with this controller.
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- #address-cells: Address representation for root ports (must be 3)
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- pinctrl-names : The pin control state names.
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- pinctrl-0: The "default" pinctrl state.
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- #size-cells: Size representation for root ports (must be 2)
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- ranges: Ranges for the PCI memory and I/O regions.
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- #interrupt-cells: Must be 1
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- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties.
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Please refer to the standard PCI bus binding document for a more detailed
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explanation.
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- status: either "disabled" or "okay".
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
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root ports.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
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root ports.
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- reset-gpios: GPIO specs for the reset pins.
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In addition, the device tree node must have sub-nodes describing each PCIe port
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interface, having the following mandatory properties:
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Required properties:
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- reg: Only the first four bytes are used to refer to the correct bus number
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and device number.
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- #address-cells: Must be 3
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- #size-cells: Must be 2
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- ranges: Sub-ranges distributed from the PCIe controller node. An empty
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property is sufficient.
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- bus-range: Range of bus numbers associated with this port.
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Example for MT7621:
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pcie: pcie@1e140000 {
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compatible = "mediatek,mt7621-pci";
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reg = <0x1e140000 0x100 /* host-pci bridge registers */
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0x1e142000 0x100 /* pcie port 0 RC control registers */
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0x1e143000 0x100 /* pcie port 1 RC control registers */
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0x1e144000 0x100>; /* pcie port 2 RC control registers */
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#address-cells = <3>;
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#size-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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device_type = "pci";
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bus-range = <0 255>;
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ranges = <
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0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
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0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
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>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xF0000 0 0 1>;
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interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
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<0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
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<0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
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reset-names = "pcie0", "pcie1", "pcie2";
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clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
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clock-names = "pcie0", "pcie1", "pcie2";
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reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
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<&gpio 8 GPIO_ACTIVE_LOW>,
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<&gpio 7 GPIO_ACTIVE_LOW>;
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pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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bus-range = <0x00 0xff>;
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};
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pcie@1,0 {
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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bus-range = <0x00 0xff>;
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};
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pcie@2,0 {
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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bus-range = <0x00 0xff>;
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};
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};
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