/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC7_QM_REGS_H_
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#define ASIC_REG_TPC7_QM_REGS_H_
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/*
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*****************************************
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* TPC7_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmTPC7_QM_GLBL_CFG0 0xFC8000
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#define mmTPC7_QM_GLBL_CFG1 0xFC8004
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#define mmTPC7_QM_GLBL_PROT 0xFC8008
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#define mmTPC7_QM_GLBL_ERR_CFG 0xFC800C
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#define mmTPC7_QM_GLBL_ERR_ADDR_LO 0xFC8010
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#define mmTPC7_QM_GLBL_ERR_ADDR_HI 0xFC8014
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#define mmTPC7_QM_GLBL_ERR_WDATA 0xFC8018
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#define mmTPC7_QM_GLBL_SECURE_PROPS 0xFC801C
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#define mmTPC7_QM_GLBL_NON_SECURE_PROPS 0xFC8020
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#define mmTPC7_QM_GLBL_STS0 0xFC8024
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#define mmTPC7_QM_GLBL_STS1 0xFC8028
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#define mmTPC7_QM_PQ_BASE_LO 0xFC8060
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#define mmTPC7_QM_PQ_BASE_HI 0xFC8064
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#define mmTPC7_QM_PQ_SIZE 0xFC8068
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#define mmTPC7_QM_PQ_PI 0xFC806C
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#define mmTPC7_QM_PQ_CI 0xFC8070
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#define mmTPC7_QM_PQ_CFG0 0xFC8074
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#define mmTPC7_QM_PQ_CFG1 0xFC8078
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#define mmTPC7_QM_PQ_ARUSER 0xFC807C
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#define mmTPC7_QM_PQ_PUSH0 0xFC8080
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#define mmTPC7_QM_PQ_PUSH1 0xFC8084
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#define mmTPC7_QM_PQ_PUSH2 0xFC8088
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#define mmTPC7_QM_PQ_PUSH3 0xFC808C
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#define mmTPC7_QM_PQ_STS0 0xFC8090
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#define mmTPC7_QM_PQ_STS1 0xFC8094
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#define mmTPC7_QM_PQ_RD_RATE_LIM_EN 0xFC80A0
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#define mmTPC7_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xFC80A4
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#define mmTPC7_QM_PQ_RD_RATE_LIM_SAT 0xFC80A8
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#define mmTPC7_QM_PQ_RD_RATE_LIM_TOUT 0xFC80AC
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#define mmTPC7_QM_CQ_CFG0 0xFC80B0
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#define mmTPC7_QM_CQ_CFG1 0xFC80B4
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#define mmTPC7_QM_CQ_ARUSER 0xFC80B8
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#define mmTPC7_QM_CQ_PTR_LO 0xFC80C0
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#define mmTPC7_QM_CQ_PTR_HI 0xFC80C4
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#define mmTPC7_QM_CQ_TSIZE 0xFC80C8
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#define mmTPC7_QM_CQ_CTL 0xFC80CC
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#define mmTPC7_QM_CQ_PTR_LO_STS 0xFC80D4
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#define mmTPC7_QM_CQ_PTR_HI_STS 0xFC80D8
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#define mmTPC7_QM_CQ_TSIZE_STS 0xFC80DC
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#define mmTPC7_QM_CQ_CTL_STS 0xFC80E0
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#define mmTPC7_QM_CQ_STS0 0xFC80E4
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#define mmTPC7_QM_CQ_STS1 0xFC80E8
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#define mmTPC7_QM_CQ_RD_RATE_LIM_EN 0xFC80F0
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#define mmTPC7_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xFC80F4
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#define mmTPC7_QM_CQ_RD_RATE_LIM_SAT 0xFC80F8
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#define mmTPC7_QM_CQ_RD_RATE_LIM_TOUT 0xFC80FC
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#define mmTPC7_QM_CQ_IFIFO_CNT 0xFC8108
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#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO 0xFC8120
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#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI 0xFC8124
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#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO 0xFC8128
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#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI 0xFC812C
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#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO 0xFC8130
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#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI 0xFC8134
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#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO 0xFC8138
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#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI 0xFC813C
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#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET 0xFC8140
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#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xFC8144
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#define mmTPC7_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xFC8148
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#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xFC814C
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#define mmTPC7_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xFC8150
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#define mmTPC7_QM_CP_LDMA_COMMIT_OFFSET 0xFC8154
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#define mmTPC7_QM_CP_FENCE0_RDATA 0xFC8158
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#define mmTPC7_QM_CP_FENCE1_RDATA 0xFC815C
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#define mmTPC7_QM_CP_FENCE2_RDATA 0xFC8160
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#define mmTPC7_QM_CP_FENCE3_RDATA 0xFC8164
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#define mmTPC7_QM_CP_FENCE0_CNT 0xFC8168
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#define mmTPC7_QM_CP_FENCE1_CNT 0xFC816C
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#define mmTPC7_QM_CP_FENCE2_CNT 0xFC8170
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#define mmTPC7_QM_CP_FENCE3_CNT 0xFC8174
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#define mmTPC7_QM_CP_STS 0xFC8178
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#define mmTPC7_QM_CP_CURRENT_INST_LO 0xFC817C
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#define mmTPC7_QM_CP_CURRENT_INST_HI 0xFC8180
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#define mmTPC7_QM_CP_BARRIER_CFG 0xFC8184
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#define mmTPC7_QM_CP_DBG_0 0xFC8188
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#define mmTPC7_QM_PQ_BUF_ADDR 0xFC8300
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#define mmTPC7_QM_PQ_BUF_RDATA 0xFC8304
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#define mmTPC7_QM_CQ_BUF_ADDR 0xFC8308
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#define mmTPC7_QM_CQ_BUF_RDATA 0xFC830C
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#endif /* ASIC_REG_TPC7_QM_REGS_H_ */
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