/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#include "halbb_precomp.h"
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bool halbb_chk_bb_rf_pkg_set_valid(struct bb_info *bb)
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{
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struct rtw_hal_com_t *hal_i = bb->hal_com;
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u8 bb_ver = 0; /*hal_i->bb_para_pkg_ver;*/ /*TBD*/
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u8 rf_ver = 0; /*hal_i->rf_para_pkg_ver;*/ /*TBD*/
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bool valid = true;
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switch (bb->ic_type) {
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#ifdef BB_8852A_CAV_SUPPORT
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case BB_RTL8852AA:
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valid = halbb_chk_pkg_valid_8852a(bb, bb_ver, rf_ver);
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break;
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#endif
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#ifdef BB_8852A_2_SUPPORT
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case BB_RTL8852A:
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valid = halbb_chk_pkg_valid_8852a_2(bb, bb_ver, rf_ver);
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break;
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#endif
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#ifdef BB_8852B_SUPPORT
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case BB_RTL8852B:
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valid = halbb_chk_pkg_valid_8852b(bb, bb_ver, rf_ver);
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break;
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#endif
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#ifdef BB_8852C_SUPPORT
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case BB_RTL8852C:
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valid = halbb_chk_pkg_valid_8852c(bb, bb_ver, rf_ver);
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break;
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#endif
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#ifdef BB_8834A_SUPPORT
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case BB_RTL8834A:
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valid = halbb_chk_pkg_valid_8834a(bb, bb_ver, rf_ver);
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break;
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#endif
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default:
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break;
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}
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return valid;
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}
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void halbb_ic_hw_setting_init(struct bb_info *bb)
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{
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#ifdef HALBB_TDMA_CR_SUPPORT
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halbb_tdma_cr_sel_init(bb);
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#endif
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switch (bb->ic_type) {
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#ifdef BB_8852A_CAV_SUPPORT
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case BB_RTL8852AA:
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halbb_ic_hw_setting_init_8852a(bb);
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break;
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#endif
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#ifdef BB_8852A_2_SUPPORT
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case BB_RTL8852A:
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halbb_ic_hw_setting_init_8852a_2(bb);
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#ifdef HALBB_DYN_CSI_RSP_SUPPORT
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halbb_dcr_init(bb);
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#endif
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#ifdef BB_DYN_CFO_TRK_LOP
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halbb_dyn_cfo_trk_loop_init(bb);
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#endif
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break;
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#endif
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#ifdef BB_8852B_SUPPORT
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case BB_RTL8852B:
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halbb_ic_hw_setting_init_8852b(bb);
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#ifdef HALBB_DYN_CSI_RSP_SUPPORT
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halbb_dcr_init(bb);
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#endif
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break;
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#endif
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#ifdef BB_8852C_SUPPORT
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case BB_RTL8852C:
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halbb_ic_hw_setting_init_8852c(bb);
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#ifdef HALBB_DYN_CSI_RSP_SUPPORT
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halbb_dcr_init(bb);
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#endif
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break;
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#endif
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default:
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break;
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}
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}
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void halbb_get_efuse_init(struct bb_info *bb)
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{
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switch (bb->ic_type) {
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#ifdef BB_8852A_2_SUPPORT
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case BB_RTL8852A:
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halbb_get_normal_efuse_init_8852a_2(bb);
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halbb_get_hidden_efuse_init_8852a_2(bb);
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break;
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#endif
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#ifdef BB_8852B_SUPPORT
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case BB_RTL8852B:
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halbb_get_normal_efuse_init_8852b(bb);
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halbb_get_hide_efuse_init_8852b(bb);
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break;
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#endif
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#ifdef BB_8852C_SUPPORT
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case BB_RTL8852C:
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halbb_get_normal_efuse_init_8852c(bb);
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halbb_get_hidden_efuse_init_8852c(bb);
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break;
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#endif
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default:
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break;
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}
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}
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void halbb_cmn_info_self_init(struct bb_info *bb)
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{
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struct rtw_hal_com_t *hal_i = bb->hal_com;
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/*[IC type]*/
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if (hal_i->chip_id == CHIP_WIFI6_8852A) {
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if (hal_i->cv == CAV)
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bb->ic_type = BB_RTL8852AA;
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else
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bb->ic_type = BB_RTL8852A;
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} else if (hal_i->chip_id == CHIP_WIFI6_8852B) {
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bb->ic_type = BB_RTL8852B;
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#ifdef BB_8852C_SUPPORT
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} else if (hal_i->chip_id == CHIP_WIFI6_8852C) {
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bb->ic_type = BB_RTL8852C;
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#endif
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} else if (hal_i->chip_id == CHIP_WIFI6_8834A) {
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bb->ic_type = BB_RTL8834A;
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#ifdef BB_8192XB_SUPPORT
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} else if (hal_i->chip_id == CHIP_WIFI6_8192XB) {
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bb->ic_type = BB_RTL8192XB;
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#endif
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}
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/*[CR type]*/
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if (bb->ic_type == BB_RTL8852AA)
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bb->cr_type = BB_52AA;
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else if (bb->ic_type & BB_IC_AX_AP)
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bb->cr_type = BB_AP;
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else if (bb->ic_type & BB_IC_AX_AP2)
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bb->cr_type = BB_AP2;
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else if (bb->ic_type & BB_IC_AX_CLIENT)
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bb->cr_type = BB_CLIENT;
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/*[RF path number]*/
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if (bb->ic_type & BB_IC_1SS)
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bb->num_rf_path = 1;
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else if (bb->ic_type & BB_IC_2SS)
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bb->num_rf_path = 2;
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else if (bb->ic_type & BB_IC_3SS)
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bb->num_rf_path = 3;
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else if (bb->ic_type & BB_IC_4SS)
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bb->num_rf_path = 4;
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else
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bb->num_rf_path = 1;
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BB_DBG(bb, DBG_INIT, "cr_type=%d, num_rf_path=%d\n",
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bb->cr_type, bb->num_rf_path);
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BB_DBG(bb, DBG_INIT,
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"num_rf_path=%d, rate_num{Legcy, HT, VHT, HE}={%d,%d,%d,%d}\n",
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bb->num_rf_path,
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LEGACY_RATE_NUM, HT_RATE_NUM, VHT_RATE_NUM, HE_RATE_NUM);
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bb->manual_support_ability = 0xffffffff;
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bb->bb_dm_init_ready = false;
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bb->bb_sys_up_time = 0;
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bb->bb_watchdog_en = true;
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bb->bb_ic_api_en = true;
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/*[Drv Dbg Info]*/
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bb->cmn_dbg_msg_period = 2;
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bb->cmn_dbg_msg_cnt = 0;
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/*[Dummy]*/
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bb->bool_dummy = false;
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bb->u8_dummy = 0xff;
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bb->u16_dummy = 0xffff;
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bb->u32_dummy = 0xffffffff;
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/*@=== [HALBB Structure] ============================================*/
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bb->bb_link_i.is_linked = false;
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bb->bb_link_i.is_linked_pre = false;
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bb->bb_link_i.tp_active_th = 5;
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bb->bb_path_i.rx_path_en = bb->num_rf_path;
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bb->bb_path_i.tx_path_en = bb->num_rf_path;
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bb->adv_bb_dm_en = true;
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bb->bb_cmn_info_init_ready = true;
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bb->bb_watchdog_period = 2; /*sec*/
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bb->bb_cmn_hooker->bb_dm_number = sizeof(halbb_func_i) / sizeof(struct halbb_func_info);
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halbb_edcca_dev_hw_cap(bb);
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halbb_cmn_info_self_reset(bb);
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}
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u64 halbb_supportability_default(struct bb_info *bb)
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{
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u64 support_ability = 0;
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switch (bb->ic_type) {
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#ifdef BB_8852A_CAV_SUPPORT
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case BB_RTL8852AA:
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support_ability |=
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/*BB_RA |*/
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BB_FA_CNT |
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/*BB_DFS |*/
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BB_EDCCA |
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/*BB_ENVMNTR |*/
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BB_CFO_TRK |
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/*BB_DIG |*/
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0;
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break;
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#endif
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#ifdef BB_8852A_2_SUPPORT
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case BB_RTL8852A:
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support_ability |=
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/*BB_RA |*/
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BB_FA_CNT |
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BB_DFS |
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BB_EDCCA |
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BB_ENVMNTR |
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BB_CFO_TRK |
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BB_DIG |
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/*BB_ANT_DIV |*/
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0;
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break;
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#endif
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#ifdef BB_8852B_SUPPORT
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case BB_RTL8852B:
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support_ability |=
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BB_RA |
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BB_FA_CNT |
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BB_DFS |
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BB_EDCCA |
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BB_CFO_TRK |
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BB_ENVMNTR |
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BB_DIG |
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0;
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break;
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#endif
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#ifdef BB_8852C_SUPPORT
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case BB_RTL8852C:
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support_ability |=
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/*BB_RA |*/
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BB_FA_CNT |
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BB_DFS |
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BB_EDCCA |
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BB_ENVMNTR |
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BB_CFO_TRK |
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BB_DIG |
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/*BB_ANT_DIV |*/
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0;
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break;
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#endif
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default:
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BB_WARNING("[%s]\n", __func__);
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break;
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}
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return support_ability;
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}
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void halbb_supportability_init(struct bb_info *bb)
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{
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u64 support_ability;
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#if 0
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if (bb->phl_com->bb_ability_manual != 0xffffffff) {
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support_ability = bb->phl_com->bb_ability_manual;
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} else
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#endif
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if(phl_is_mp_mode(bb->phl_com)) {
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support_ability = 0;
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} else {
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support_ability = halbb_supportability_default(bb);
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}
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bb->support_ability = support_ability;
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BB_DBG(bb, DBG_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
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bb->ic_type, bb->phl_com->drv_mode, bb->support_ability);
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}
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void halbb_hw_init(struct bb_info *bb)
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{
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BB_DBG(bb, DBG_INIT, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx);
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halbb_cmn_info_self_init(bb);
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if (!halbb_chk_bb_rf_pkg_set_valid(bb)) {
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BB_WARNING("[%s] Init fail\n", __func__);
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return;
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}
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}
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void halbb_dm_deinit(struct rtw_phl_com_t *phl_com, void *bb_phy_0)
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{
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struct bb_info *bb = (struct bb_info *)bb_phy_0;
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if (!bb->bb_dm_init_ready)
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return;
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halbb_timer_ctrl(bb, BB_CANCEL_TIMER);
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#ifdef HALBB_LA_MODE_SUPPORT
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halbb_la_deinit(bb);
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#endif
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#ifdef HALBB_PSD_SUPPORT
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halbb_psd_deinit(bb);
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#endif
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#ifdef HALBB_CH_INFO_SUPPORT
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halbb_ch_info_deinit(bb);
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#endif
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#ifdef HALBB_DIG_SUPPORT
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halbb_dig_deinit(bb);
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#endif
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#ifdef HALBB_ANT_DIV_SUPPORT
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halbb_antdiv_deinit(bb);
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#endif
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#ifdef BB_8852A_2_SUPPORT
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#endif
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#ifdef HALBB_CFO_TRK_SUPPORT
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halbb_cfo_deinit(bb);
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#endif
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bb->bb_dm_init_ready = false;
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}
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enum rtw_hal_status halbb_dm_init(struct bb_info *bb, enum phl_phy_idx phy_idx)
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{
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enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
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if (!bb) {
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BB_WARNING("[%s] *bb = NULL", __func__);
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return RTW_HAL_STATUS_FAILURE;
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}
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if (!bb->bb_cmn_info_init_ready) {
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BB_WARNING("bb_cmn_info_init_ready = false");
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return RTW_HAL_STATUS_FAILURE;
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}
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#ifdef HALBB_DBCC_SUPPORT
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#ifdef HALBB_DBCC_DVLP_FLAG
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if (phy_idx == HW_PHY_1)
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return hal_status;
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#endif
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bb = halbb_get_curr_bb_pointer(bb, phy_idx);
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BB_DBG(bb, DBG_INIT, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx);
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#endif
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halbb_ic_hw_setting_init(bb);
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halbb_gpio_setting_init(bb);
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halbb_get_efuse_init(bb);
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halbb_supportability_init(bb);
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halbb_physts_parsing_init(bb);
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halbb_cmn_rpt_init(bb);
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halbb_dbg_setting_init(bb);
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#ifdef HALBB_PWR_CTRL_SUPPORT
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halbb_macid_ctrl_init(bb);
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#endif
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#ifdef HALBB_STATISTICS_SUPPORT
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halbb_statistics_init(bb);
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#endif
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#ifdef HALBB_LA_MODE_SUPPORT
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halbb_la_init(bb);
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#endif
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#ifdef HALBB_PSD_SUPPORT
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halbb_psd_init(bb);
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#endif
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#ifdef HALBB_EDCCA_SUPPORT
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halbb_edcca_init(bb);
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#endif
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#ifdef HALBB_DFS_SUPPORT
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halbb_dfs_init(bb);
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#endif
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#ifdef HALBB_DIG_SUPPORT
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halbb_dig_init(bb);
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#endif
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#ifdef HALBB_CFO_TRK_SUPPORT
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halbb_cfo_trk_init(bb);
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#endif
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#ifdef HALBB_RA_SUPPORT
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halbb_ra_init(bb);
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#endif
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#ifdef HALBB_ENV_MNTR_SUPPORT
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halbb_env_mntr_init(bb);
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#endif
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#ifdef HALBB_PWR_CTRL_SUPPORT
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halbb_pwr_ctrl_init(bb);
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#endif
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#ifdef HALBB_RUA_SUPPORT
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halbb_rua_tbl_init(bb);
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#endif
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#ifdef HALBB_ANT_DIV_SUPPORT
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halbb_antdiv_init(bb);
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#endif
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#ifdef HALBB_CH_INFO_SUPPORT
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halbb_ch_info_init(bb);
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#endif
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halbb_reset_adc(bb);
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#ifdef HALBB_DIG_MCC_SUPPORT
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Halbb_init_mccdm(bb);
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#endif
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bb->bb_dm_init_ready = true;
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BB_DBG(bb, DBG_INIT, "bb_init_ready = %d\n", bb->bb_dm_init_ready);
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return hal_status;
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}
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void halbb_timer_ctrl(struct bb_info *bb, enum bb_timer_cfg_t timer_state)
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{
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BB_DBG(bb, DBG_INIT, "[%s] timer_state = %d\n", __func__, timer_state);
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/*BB-0 & BB-1 timer*/
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#ifdef HALBB_ANT_DIV_SUPPORT
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halbb_cfg_timers(bb, timer_state, &bb->bb_ant_div_i.antdiv_timer_i);
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#endif
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#ifdef HALBB_CFO_TRK_SUPPORT
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halbb_cfg_timers(bb, timer_state, &bb->bb_cfo_trk_i.cfo_timer_i);
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#endif
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#ifdef HALBB_TDMA_CR_SUPPORT
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halbb_cfg_timers(bb, timer_state, &bb->bb_dbg_i.tdma_cr_timer_i);
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#endif
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#ifdef HALBB_DIG_TDMA_SUPPORT
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halbb_cfg_timers(bb, timer_state, &bb->bb_dig_i.dig_timer_i);
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#endif
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if (!bb->bb_cmn_hooker)
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return;
|
|
/*BB Common Timer*/
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#ifdef HALBB_LA_MODE_SUPPORT
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halbb_cfg_timers(bb, timer_state, &bb->bb_cmn_hooker->bb_la_mode_i.la_timer_i);
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#endif
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}
|
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void halbb_timer_init(struct bb_info *bb)
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{
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BB_DBG(bb, DBG_INIT, "[%s]\n", __func__);
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|
#ifdef HALBB_ANT_DIV_SUPPORT
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halbb_antdiv_timer_init(bb);
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#endif
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#ifdef HALBB_CFO_TRK_SUPPORT
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halbb_cfo_acc_timer_init(bb);
|
#endif
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#ifdef HALBB_TDMA_CR_SUPPORT
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halbb_tdma_cr_timer_init(bb);
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#endif
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#ifdef HALBB_DIG_TDMA_SUPPORT
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halbb_dig_timer_init(bb);
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#endif
|
#ifdef HALBB_LA_MODE_SUPPORT
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halbb_la_timer_init(bb);
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#endif
|
}
|
|
void halbb_cr_cfg_init(struct bb_info *bb)
|
{
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halbb_cr_cfg_dbg_init(bb);
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halbb_cr_cfg_physts_init(bb);
|
#ifdef HALBB_STATISTICS_SUPPORT
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halbb_cr_cfg_stat_init(bb);
|
#endif
|
#ifdef HALBB_PSD_SUPPORT
|
halbb_cr_cfg_psd_init(bb);
|
#endif
|
#ifdef HALBB_DIG_SUPPORT
|
halbb_cr_cfg_dig_init(bb);
|
#endif
|
#ifdef HALBB_ENV_MNTR_SUPPORT
|
halbb_cr_cfg_env_mntr_init(bb);
|
#endif
|
#ifdef HALBB_EDCCA_SUPPORT
|
halbb_cr_cfg_edcca_init(bb);
|
#endif
|
#ifdef HALBB_DFS_SUPPORT
|
halbb_cr_cfg_dfs_init(bb);
|
#endif
|
#ifdef HALBB_LA_MODE_SUPPORT
|
halbb_cr_cfg_la_init(bb);
|
#endif
|
#ifdef HALBB_ANT_DIV_SUPPORT
|
halbb_cr_cfg_antdiv_init(bb);
|
#endif
|
#ifdef HALBB_PMAC_TX_SUPPORT
|
halbb_cr_cfg_plcp_init(bb);
|
#endif
|
halbb_cr_cfg_mp_init(bb);
|
#ifdef HALBB_CH_INFO_SUPPORT
|
halbb_cr_cfg_ch_info_init(bb);
|
#endif
|
#ifdef HALBB_CFO_TRK_SUPPORT
|
halbb_cr_cfg_cfo_trk_init(bb);
|
#endif
|
}
|
|
void halbb_buffer_deinit(struct rtw_phl_com_t *phl_com,
|
struct rtw_hal_com_t *hal_com, void *bb_phy_0)
|
{
|
struct bb_info *bb = (struct bb_info *)bb_phy_0;
|
|
BB_DBG(bb, DBG_INIT, "deinit phy-%d", bb->bb_phy_idx);
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halbb_timer_ctrl(bb, BB_CANCEL_TIMER);
|
halbb_timer_ctrl(bb, BB_RELEASE_TIMER);
|
|
/*Deinit phy-cmn*/
|
if (bb->bb_cmn_hooker) {
|
BB_DBG(bb, DBG_INIT, "deinit bb_cmn_hooker");
|
hal_mem_free(hal_com, bb->bb_cmn_hooker, sizeof(struct bb_cmn_info));
|
}
|
#ifdef HALBB_DBCC_SUPPORT
|
/*Deinit phy-1*/
|
if (bb->bb_phy_hooker) {
|
BB_DBG(bb, DBG_INIT, "deinit phy-%d", bb->bb_phy_hooker->bb_phy_idx);
|
//halbb_timer_ctrl(bb->bb_phy_hooker, BB_CANCEL_TIMER);
|
//halbb_timer_ctrl(bb->bb_phy_hooker, BB_RELEASE_TIMER);
|
hal_mem_free(hal_com, bb->bb_phy_hooker, sizeof(struct bb_info));
|
}
|
#endif
|
/*Deinit phy-0*/
|
if (bb) {
|
hal_mem_free(hal_com, bb, sizeof(struct bb_info));
|
}
|
}
|
|
u32
|
halbb_buffer_init(struct rtw_phl_com_t *phl_com,
|
struct rtw_hal_com_t *hal_com, void **bb_out_addr)
|
{
|
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
|
struct bb_info *bb_0 = NULL;
|
struct bb_cmn_info *bb_cmn = NULL;
|
|
bb_0 = hal_mem_alloc(hal_com, sizeof(struct bb_info));
|
|
if (!bb_0) {
|
BB_WARNING("*bb = NULL\n");
|
return RTW_HAL_STATUS_BB_INIT_FAILURE;
|
}
|
|
*bb_out_addr = bb_0;
|
|
bb_0->phl_com = phl_com;/*shared memory for all components*/
|
bb_0->hal_com = hal_com;/*shared memory for phl and hal*/
|
bb_0->bb_phy_idx = HW_PHY_0;
|
|
bb_cmn = hal_mem_alloc(hal_com, sizeof(struct bb_cmn_info));
|
if (!bb_cmn) {
|
BB_WARNING("*bb_cmn = NULL\n");
|
return RTW_HAL_STATUS_BB_INIT_FAILURE;
|
}
|
|
bb_0->bb_cmn_hooker = bb_cmn;
|
|
halbb_dbg_comp_init(bb_0);
|
halbb_hw_init(bb_0);
|
halbb_timer_init(bb_0);
|
halbb_cr_cfg_init(bb_0);
|
|
#ifdef HALBB_DBCC_SUPPORT
|
BB_DBG(bb_0, DBG_INIT, "dbcc_support = %d\n", phl_com->dev_cap.dbcc_sup);
|
hal_status = halbb_buffer_init_phy1(bb_0);
|
#else
|
BB_DBG(bb_0, DBG_INIT, "DBCC macro not enabled\n");
|
#endif
|
|
BB_DBG(bb_0, DBG_INIT, "[%s]\n", __func__);
|
BB_DBG(bb_0, DBG_INIT, " %-35s: %s\n", "Code Base:", HLABB_CODE_BASE);
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BB_DBG(bb_0, DBG_INIT, " %-35s: %s\n", "Code Release Date", HALBB_RELEASE_DATE);
|
|
#ifdef BB_8852A_CAV_SUPPORT
|
BB_DBG(bb_0, DBG_INIT, " %-35s: %d\n", "[CAV]52A BB_REG Ver", BB_REG_RELEASE_VERSION_8852A);
|
BB_DBG(bb_0, DBG_INIT, " %-35s: %d\n", "[CAV]52A BB_REG Release Date", BB_REG_RELEASE_DATE_8852A);
|
#endif
|
|
#ifdef BB_8852A_2_SUPPORT
|
BB_DBG(bb_0, DBG_INIT, " %-35s: %d\n", "[>CBV]52A BB_REG Ver", BB_REG_RELEASE_VERSION_8852A_2);
|
BB_DBG(bb_0, DBG_INIT, " %-35s: %d\n", "[>CBV]52A BB_REG Release Date", BB_REG_RELEASE_DATE_8852A_2);
|
#endif
|
|
return (u32)hal_status;
|
}
|
