/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_PWR_CTRL_H__
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#define __HALBB_PWR_CTRL_H__
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/*@--------------------------[Define] ---------------------------------------*/
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#define REG_PWRMACID_OFST 0x0016c
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#define HALBB_PWR_STATE_NUM 3
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#define DTP_FLOOR_UP_GAP 3
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#define TX_HP_LV_0 0
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#define TX_HP_LV_1 1
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#define TX_HP_LV_2 2
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#define TX_HP_LV_3 3
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#define TX_HP_LV_UNCHANGE 4
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/*#if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
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#define TX_PWR_TH_LVL3 87
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#define TX_PWR_TH_LVL2 78
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#define TX_PWR_TH_LVL1 70
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/*#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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#define TX_PWR_TH_LVL3 90
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#define TX_PWR_TH_LVL2 85
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#define TX_PWR_TH_LVL1 80
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#endif*/
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#define TX_PWR_LVL3 6 /*3dBm*/
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#define TX_PWR_LVL2 12 /*6dBm*/
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#define TX_PWR_LVL1 20 /*10dBm*/
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/*@--------------------------[Enum]------------------------------------------*/
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/*@--------------------------[Structure]-------------------------------------*/
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/* @ Dynamic CCA TH part */
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struct bb_macidcca_info {
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bool cca_th_en;
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s8 cca_th;
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};
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struct bb_dyncca_info {
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/* [] */
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bool dyncca_en;
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u8 dyncca_offset;
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u8 dyncca_offset_n;
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/**/
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struct bb_macidcca_info macidcca_i[PHL_MAX_STA_NUM];
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};
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/* @ Power Ctrl part */
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struct bb_dtp_info {
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/*u8 dyn_tx_power;
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u8 last_tx_power;*/
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u8 dyn_tx_pwr_lvl:4;
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u8 last_pwr_lvl:4;
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s8 pwr_val[2]; /* S(8,1) */
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bool en_pwr[2];
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};
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struct bb_pwr_ctrl_info {
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u8 pwr;
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/* [] */
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u8 enhance_pwr_th[HALBB_PWR_STATE_NUM];
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u8 set_pwr_th[HALBB_PWR_STATE_NUM];
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u8 pwr_lv_dbm[HALBB_PWR_STATE_NUM];
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/**/
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struct bb_dtp_info dtp_i[PHL_MAX_STA_NUM];
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};
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struct bb_info;
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/*@--------------------------[Prptotype]-------------------------------------*/
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#ifdef HALBB_PWR_CTRL_SUPPORT
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void halbb_pwr_ctrl(struct bb_info *bb);
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void halbb_pwr_ctrl_init(struct bb_info *bb);
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void halbb_set_pwr_macid_idx(struct bb_info *bb, u16 macid, s8 pwr, bool pwr_en, u8 idx);
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#endif
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void halbb_macid_ctrl_init(struct bb_info *bb);
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void halbb_tpu_mac_cr_init(struct bb_info *bb, enum phl_phy_idx phy_idx);
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void halbb_pwr_dbg(struct bb_info *bb, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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#endif
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