/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_IC_HW_INFO_H__
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#define __HALBB_IC_HW_INFO_H__
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enum bb_ic_t {
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BB_RTL8852AA = BIT(0), /*8852A Acut*/
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BB_RTL8852A = BIT(1), /*8852A > Bcut*/
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BB_RTL8852B = BIT(2),
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BB_RTL8852C = BIT(3),
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BB_RTL8834A = BIT(4),
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BB_RTL8192XB = BIT(5)
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};
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enum bb_cr_t {
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BB_52AA = 0,
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BB_AP = 1,
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BB_AP2 = 2,
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BB_CLIENT = 3
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};
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#define BB_IC_N_1SS 0
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#define BB_IC_N_2SS 0
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#define BB_IC_N_3SS 0
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#define BB_IC_N_4SS 0
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#define BB_IC_AC_1SS 0
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#define BB_IC_AC_2SS 0
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#define BB_IC_AC_3SS 0
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#define BB_IC_AC_4SS 0
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#define BB_IC_AX_1SS 0
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#define BB_IC_AX_2SS (BB_RTL8852AA | BB_RTL8852A | BB_RTL8852B | BB_RTL8852C)
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#define BB_IC_AX_3SS 0
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#define BB_IC_AX_4SS (BB_RTL8834A)
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/*@====the following macro DO NOT need to update when adding a new IC======= */
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#define BB_IC_1SS (BB_IC_N_1SS | BB_IC_AC_1SS | BB_IC_AX_1SS)
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#define BB_IC_2SS (BB_IC_N_2SS | BB_IC_AC_2SS | BB_IC_AX_2SS)
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#define BB_IC_3SS (BB_IC_N_3SS | BB_IC_AC_3SS | BB_IC_AX_3SS)
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#define BB_IC_4SS (BB_IC_N_4SS | BB_IC_AC_4SS | BB_IC_AX_4SS)
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#define BB_IC_ABOVE_1SS (BB_IC_1SS | BB_IC_2SS | BB_IC_3SS |\
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BB_IC_4SS)
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#define BB_IC_ABOVE_2SS (BB_IC_2SS | BB_IC_3SS | BB_IC_4SS)
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#define BB_IC_ABOVE_3SS (BB_IC_3SS | BB_IC_4SS)
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#define BB_IC_ABOVE_4SS BB_IC_4SS
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#define BB_IC_N_SERIES (BB_IC_N_1SS | BB_IC_N_2SS | BB_IC_N_3SS |\
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BB_IC_N_4SS)
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#define BB_IC_AC_SERIES (BB_IC_AC_1SS | BB_IC_AC_2SS |\
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BB_IC_AC_3SS | BB_IC_AC_4SS)
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#define BB_IC_AX_SERIES (BB_IC_AX_1SS | BB_IC_AX_2SS |\
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BB_IC_AX_3SS | BB_IC_AX_4SS)
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/*@==========================================================================*/
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#define BB_IC_AX_AP (BB_RTL8852AA | BB_RTL8852A | BB_RTL8852C | BB_RTL8834A)
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#define BB_IC_AX_AP2 (BB_RTL8852C | BB_RTL8192XB)
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#define BB_IC_AX_CLIENT (BB_RTL8852B)
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/*@==========================================================================*/
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#define BB_IC_MAX_BW_80 (BB_RTL8852AA | BB_RTL8852A | BB_RTL8852B)
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#define BB_IC_MAX_BW_160 (BB_RTL8852C | BB_RTL8834A)
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/*@==========================================================================*/
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#if defined(BB_8852A_CAV_SUPPORT) || defined(BB_8852A_2_SUPPORT)
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#define HALBB_COMPILE_IC_DBCC
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#endif
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#if defined(BB_8852A_CAV_SUPPORT) || defined(BB_8852A_2_SUPPORT) || defined(BB_8852B_SUPPORT)
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/* FW OFFLOAD will be used in non-AP-only ICs*/
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#define HALBB_COMPILE_IC_FWOFLD
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#endif
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#if defined(RTL8851A_SUPPORT)
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#define HALBB_COMPILE_IC_1SS
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#endif
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#if (defined(BB_8852A_CAV_SUPPORT) || defined(BB_8852A_2_SUPPORT) || defined(BB_8852B_SUPPORT) || defined(BB_8852C_SUPPORT))
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#define HALBB_COMPILE_IC_2SS
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#endif
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#if defined(RTL8853A_SUPPORT)
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#define HALBB_COMPILE_IC_3SS
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#endif
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#if defined(RTL8834A_SUPPORT)
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#define HALBB_COMPILE_IC_4SS
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#endif
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/*@==========================================================================*/
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#if (defined(HALBB_COMPILE_IC_4SS))
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#define HALBB_COMPILE_ABOVE_4SS
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#endif
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#if (defined(HALBB_COMPILE_IC_3SS) || defined(HALBB_COMPILE_ABOVE_4SS))
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#define HALBB_COMPILE_ABOVE_3SS
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#endif
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#if (defined(HALBB_COMPILE_IC_2SS) || defined(HALBB_COMPILE_ABOVE_3SS))
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#define HALBB_COMPILE_ABOVE_2SS
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#endif
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#if (defined(HALBB_COMPILE_IC_1SS) || defined(HALBB_COMPILE_ABOVE_2SS))
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#define HALBB_COMPILE_ABOVE_1SS
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#endif
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#if (defined(HALBB_COMPILE_ABOVE_4SS))
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#define HALBB_MAX_PATH 4
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#elif (defined(HALBB_COMPILE_ABOVE_3SS))
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#define HALBB_MAX_PATH 3
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#elif (defined(HALBB_COMPILE_ABOVE_2SS))
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#define HALBB_MAX_PATH 2
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#else
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#define HALBB_MAX_PATH 1
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#endif
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/*@==========================================================================*/
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#if (defined(BB_8852A_CAV_SUPPORT))
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#define HALBB_52AA_SERIES
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#endif
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#if (defined(BB_8852A_2_SUPPORT) || defined(BB_8852C_SUPPORT) || defined(BB_8834A_SUPPORT))
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#define HALBB_COMPILE_AP_SERIES
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#endif
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#if (defined(BB_8852C_SUPPORT) || defined(BB_8192XB_SUPPORT))
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#define HALBB_COMPILE_AP2_SERIES
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#endif
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#if (defined(BB_8852B_SUPPORT))
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#define HALBB_COMPILE_CLIENT_SERIES
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#endif
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/*@==========================================================================*/
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enum halbb_rate_type {
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BB_1SS = 1, /*HE/VHT/HT 1SS*/
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BB_2SS = 2, /*HE/VHT/HT 2SS*/
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BB_3SS = 3, /*HE/VHT/HT 3SS*/
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BB_4SS = 4, /*HE/VHT/HT 4SS*/
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BB_CCK = 11, /*B mode*/
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BB_OFDM = 12 /*G mode*/
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};
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enum halbb_rate_table {
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BB_01M = 0,
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BB_02M = 1,
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BB_05M = 2,
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BB_11M = 3,
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BB_06M = 4,
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BB_09M = 5,
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BB_12M = 6,
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BB_18M = 7,
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BB_24M = 8,
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BB_36M = 9,
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BB_48M = 10,
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BB_54M = 11,
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BB_HT_MCS0 = 128, /*0x1000000*/
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BB_VHT_1SS_MCS0 = 256, /*0x2000000*/
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BB_VHT_2SS_MCS0 = 272,
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BB_VHT_3SS_MCS0 = 288,
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BB_VHT_4SS_MCS0 = 304,
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BB_VHT_5SS_MCS0 = 320,
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BB_VHT_6SS_MCS0 = 336,
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BB_VHT_7SS_MCS0 = 352,
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BB_VHT_8SS_MCS0 = 368,
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BB_HE_1SS_MCS0 = 384, /*0x3000000*/
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BB_HE_2SS_MCS0 = 400,
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BB_HE_3SS_MCS0 = 416,
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BB_HE_4SS_MCS0 = 432,
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BB_HE_5SS_MCS0 = 448,
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BB_HE_6SS_MCS0 = 464,
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BB_HE_7SS_MCS0 = 480,
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BB_HE_8SS_MCS0 = 496
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};
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enum halbb_legacy_spec_rate {
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BB_SPEC_RATE_6M = 0xb,
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BB_SPEC_RATE_9M = 0xf,
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BB_SPEC_RATE_12M = 0xa,
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BB_SPEC_RATE_18M = 0xe,
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BB_SPEC_RATE_24M = 0x9,
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BB_SPEC_RATE_36M = 0xd,
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BB_SPEC_RATE_48M = 0x8,
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BB_SPEC_RATE_54M = 0xc
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};
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#define GEN_HT_RATE_IDX(MCS) (0x80 | ((MCS) & 0x1f))
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#define GEN_VHT_RATE_IDX(SS, MCS) (0x100 | (((SS) & 0x3) << 4) | ((MCS) & 0xf))
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#define GEN_HE_RATE_IDX(SS, MCS) (0x180 | (((SS) & 0x3) << 4) | ((MCS) & 0xf))
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#define BB_HT_MCS(x) (BB_HT_MCS0 + x)
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#define BB_VHT_1SS_MCS(x) (BB_VHT_1SS_MCS0 + x)
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#define BB_VHT_2SS_MCS(x) (BB_VHT_2SS_MCS0 + x)
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#define BB_VHT_3SS_MCS(x) (BB_VHT_3SS_MCS0 + x)
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#define BB_VHT_4SS_MCS(x) (BB_VHT_4SS_MCS0 + x)
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#define BB_VHT_5SS_MCS(x) (BB_VHT_5SS_MCS0 + x)
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#define BB_VHT_6SS_MCS(x) (BB_VHT_6SS_MCS0 + x)
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#define BB_VHT_7SS_MCS(x) (BB_VHT_7SS_MCS0 + x)
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#define BB_VHT_8SS_MCS(x) (BB_VHT_8SS_MCS0 + x)
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#define BB_HE_1SS_MCS(x) (BB_HE_1SS_MCS0 + x)
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#define BB_HE_2SS_MCS(x) (BB_HE_2SS_MCS0 + x)
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#define BB_HE_3SS_MCS(x) (BB_HE_3SS_MCS0 + x)
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#define BB_HE_4SS_MCS(x) (BB_HE_4SS_MCS0 + x)
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#define BB_HE_5SS_MCS(x) (BB_HE_5SS_MCS0 + x)
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#define BB_HE_6SS_MCS(x) (BB_HE_6SS_MCS0 + x)
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#define BB_HE_7SS_MCS(x) (BB_HE_7SS_MCS0 + x)
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#define BB_HE_8SS_MCS(x) (BB_HE_8SS_MCS0 + x)
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#define BB_VHT_MCS(SS, x) (BB_VHT_1SS_MCS0 + ((SS - 1) * 16 ) + x)
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#define BB_HE_MCS(SS, x) (BB_HE_1SS_MCS0 + ((SS - 1) * 16 ) + x)
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/*[Rate Number]*/
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#define HT_NUM_MCS 8
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#define HE_VHT_NUM_MCS 12
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#define LEGACY_RATE_NUM 12
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#define HT_RATE_NUM_4SS (HT_NUM_MCS * 4)
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#define VHT_RATE_NUM_4SS (HE_VHT_NUM_MCS * 4)
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#define HE_RATE_NUM_4SS (HE_VHT_NUM_MCS * 4)
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#define HT_RATE_NUM_3SS (HT_NUM_MCS * 3)
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#define VHT_RATE_NUM_3SS (HE_VHT_NUM_MCS * 3)
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#define HE_RATE_NUM_3SS (HE_VHT_NUM_MCS * 3)
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#define HT_RATE_NUM_2SS (HT_NUM_MCS * 2)
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#define VHT_RATE_NUM_2SS (HE_VHT_NUM_MCS * 2)
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#define HE_RATE_NUM_2SS (HE_VHT_NUM_MCS * 2)
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#define HT_RATE_NUM_1SS HT_NUM_MCS
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#define VHT_RATE_NUM_1SS HE_VHT_NUM_MCS
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#define HE_RATE_NUM_1SS HE_VHT_NUM_MCS
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#if (defined(HALBB_COMPILE_ABOVE_4SS))
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#define HT_RATE_NUM HT_RATE_NUM_4SS
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#define VHT_RATE_NUM VHT_RATE_NUM_4SS
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#define HE_RATE_NUM HE_RATE_NUM_4SS
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#elif (defined(HALBB_COMPILE_ABOVE_3SS))
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#define HT_RATE_NUM HT_RATE_NUM_3SS
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#define VHT_RATE_NUM VHT_RATE_NUM_3SS
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#define HE_RATE_NUM HE_RATE_NUM_3SS
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#elif (defined(HALBB_COMPILE_ABOVE_2SS))
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#define HT_RATE_NUM HT_RATE_NUM_2SS
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#define VHT_RATE_NUM VHT_RATE_NUM_2SS
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#define HE_RATE_NUM HE_RATE_NUM_2SS
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#else
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#define HT_RATE_NUM HT_RATE_NUM_1SS
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#define VHT_RATE_NUM VHT_RATE_NUM_1SS
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#define HE_RATE_NUM HE_RATE_NUM_1SS
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#endif
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#define LOW_BW_RATE_NUM HE_RATE_NUM
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/*@==========================================================================*/
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/****************************************************************
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* 1 ============================================================
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* 1 enumeration
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* 1 ============================================================
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***************************************************************/
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enum bb_qam_type {
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BB_QAM_CCK = 0,
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BB_QAM_BPSK = 1,
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BB_QAM_QPSK = 2,
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BB_QAM_16QAM = 3,
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BB_QAM_64QAM = 4,
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BB_QAM_256QAM = 5,
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BB_QAM_1024QAM = 6
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};
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enum bb_mode_type { /*@Fast antenna training*/
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BB_LEGACY_MODE = 0,
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BB_HT_MODE = 1,
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BB_VHT_MODE = 2,
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BB_HE_MODE = 3
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};
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/* BB_CMNINFO_CART_VER */
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enum halbb_cart_ver {
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BB_CART_A = 0,
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BB_CART_B = 1,
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BB_CART_C = 2,
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BB_CART_D = 3,
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BB_CART_E = 4,
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BB_CART_F = 5,
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BB_CART_G = 6,
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BB_CART_H = 7,
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BB_CART_I = 8,
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BB_CART_J = 9,
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BB_CART_K = 10,
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BB_CART_L = 11,
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BB_CART_M = 12,
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BB_CART_N = 13,
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BB_CART_O = 14,
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BB_CART_TEST = 15,
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};
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enum bb_path {
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BB_PATH_NON = 0,
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BB_PATH_A = 0x00000001,
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BB_PATH_B = 0x00000002,
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BB_PATH_C = 0x00000004,
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BB_PATH_D = 0x00000008,
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BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
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BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
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BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
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BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
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BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
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BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
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BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
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BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
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BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
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BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
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BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
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BB_PATH_AUTO = 0xff /*for auto path selection*/
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};
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enum rf_syn {
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RF_SYN0 = 0,
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RF_SYN1 = 1,
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};
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#endif
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