/*
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* Copyright (c) 2010 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _BRCM_TYPES_H_
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#define _BRCM_TYPES_H_
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#include <linux/types.h>
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#include <linux/io.h>
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#define WL_CHAN_FREQ_RANGE_2G 0
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#define WL_CHAN_FREQ_RANGE_5GL 1
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#define WL_CHAN_FREQ_RANGE_5GM 2
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#define WL_CHAN_FREQ_RANGE_5GH 3
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/* boardflags */
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/* Board has gpio 9 controlling the PA */
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#define BFL_PACTRL 0x00000002
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/* Not ok to power down the chip pll and oscillator */
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#define BFL_NOPLLDOWN 0x00000020
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/* Board supports the Front End Module */
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#define BFL_FEM 0x00000800
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/* Board has an external LNA in 2.4GHz band */
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#define BFL_EXTLNA 0x00001000
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/* Board has no PA */
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#define BFL_NOPA 0x00010000
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/* Power topology uses BUCKBOOST */
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#define BFL_BUCKBOOST 0x00200000
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/* Board has FEM and switch to share antenna w/ BT */
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#define BFL_FEM_BT 0x00400000
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/* Power topology doesn't use CBUCK */
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#define BFL_NOCBUCK 0x00800000
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/* Power topology uses PALDO */
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#define BFL_PALDO 0x02000000
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/* Board has an external LNA in 5GHz band */
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#define BFL_EXTLNA_5GHz 0x10000000
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/* boardflags2 */
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/* Board has an external rxbb regulator */
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#define BFL2_RXBB_INT_REG_DIS 0x00000001
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/* Flag to implement alternative A-band PLL settings */
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#define BFL2_APLL_WAR 0x00000002
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/* Board permits enabling TX Power Control */
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#define BFL2_TXPWRCTRL_EN 0x00000004
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/* Board supports the 2X4 diversity switch */
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#define BFL2_2X4_DIV 0x00000008
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/* Board supports 5G band power gain */
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#define BFL2_5G_PWRGAIN 0x00000010
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/* Board overrides ASPM and Clkreq settings */
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#define BFL2_PCIEWAR_OVR 0x00000020
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#define BFL2_LEGACY 0x00000080
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/* 4321mcm93 board uses Skyworks FEM */
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#define BFL2_SKWRKFEM_BRD 0x00000100
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/* Board has a WAR for clock-harmonic spurs */
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#define BFL2_SPUR_WAR 0x00000200
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/* Flag to narrow G-band PLL loop b/w */
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#define BFL2_GPLL_WAR 0x00000400
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/* Tx CCK pkts on Ant 0 only */
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#define BFL2_SINGLEANT_CCK 0x00001000
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/* WAR to reduce and avoid clock-harmonic spurs in 2G */
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#define BFL2_2G_SPUR_WAR 0x00002000
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/* Flag to widen G-band PLL loop b/w */
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#define BFL2_GPLL_WAR2 0x00010000
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#define BFL2_IPALVLSHIFT_3P3 0x00020000
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/* Use internal envelope detector for TX IQCAL */
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#define BFL2_INTERNDET_TXIQCAL 0x00040000
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/* Keep the buffered Xtal output from radio "ON". Most drivers will turn it
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* off without this flag to save power. */
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#define BFL2_XTALBUFOUTEN 0x00080000
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/*
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* board specific GPIO assignment, gpio 0-3 are also customer-configurable
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* led
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*/
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/* bit 9 controls the PA on new 4306 boards */
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#define BOARD_GPIO_PACTRL 0x200
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#define BOARD_GPIO_12 0x1000
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#define BOARD_GPIO_13 0x2000
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/* **** Core type/rev defaults **** */
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#define D11CONF 0x0fffffb0 /* Supported D11 revs: 4, 5, 7-27
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* also need to update wlc.h MAXCOREREV
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*/
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#define NCONF 0x000001ff /* Supported nphy revs:
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* 0 4321a0
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* 1 4321a1
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* 2 4321b0/b1/c0/c1
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* 3 4322a0
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* 4 4322a1
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* 5 4716a0
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* 6 43222a0, 43224a0
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* 7 43226a0
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* 8 5357a0, 43236a0
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*/
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#define LCNCONF 0x00000007 /* Supported lcnphy revs:
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* 0 4313a0, 4336a0, 4330a0
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* 1
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* 2 4330a0
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*/
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#define SSLPNCONF 0x0000000f /* Supported sslpnphy revs:
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* 0 4329a0/k0
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* 1 4329b0/4329C0
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* 2 4319a0
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* 3 5356a0
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*/
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/********************************************************************
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* Phy/Core Configuration. Defines macros to to check core phy/rev *
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* compile-time configuration. Defines default core support. *
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* ******************************************************************
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*/
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/* Basic macros to check a configuration bitmask */
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#define CONF_HAS(config, val) ((config) & (1 << (val)))
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#define CONF_MSK(config, mask) ((config) & (mask))
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#define MSK_RANGE(low, hi) ((1 << ((hi)+1)) - (1 << (low)))
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#define CONF_RANGE(config, low, hi) (CONF_MSK(config, MSK_RANGE(low, high)))
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#define CONF_IS(config, val) ((config) == (1 << (val)))
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#define CONF_GE(config, val) ((config) & (0-(1 << (val))))
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#define CONF_GT(config, val) ((config) & (0-2*(1 << (val))))
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#define CONF_LT(config, val) ((config) & ((1 << (val))-1))
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#define CONF_LE(config, val) ((config) & (2*(1 << (val))-1))
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/* Wrappers for some of the above, specific to config constants */
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#define NCONF_HAS(val) CONF_HAS(NCONF, val)
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#define NCONF_MSK(mask) CONF_MSK(NCONF, mask)
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#define NCONF_IS(val) CONF_IS(NCONF, val)
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#define NCONF_GE(val) CONF_GE(NCONF, val)
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#define NCONF_GT(val) CONF_GT(NCONF, val)
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#define NCONF_LT(val) CONF_LT(NCONF, val)
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#define NCONF_LE(val) CONF_LE(NCONF, val)
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#define LCNCONF_HAS(val) CONF_HAS(LCNCONF, val)
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#define LCNCONF_MSK(mask) CONF_MSK(LCNCONF, mask)
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#define LCNCONF_IS(val) CONF_IS(LCNCONF, val)
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#define LCNCONF_GE(val) CONF_GE(LCNCONF, val)
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#define LCNCONF_GT(val) CONF_GT(LCNCONF, val)
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#define LCNCONF_LT(val) CONF_LT(LCNCONF, val)
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#define LCNCONF_LE(val) CONF_LE(LCNCONF, val)
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#define D11CONF_HAS(val) CONF_HAS(D11CONF, val)
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#define D11CONF_MSK(mask) CONF_MSK(D11CONF, mask)
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#define D11CONF_IS(val) CONF_IS(D11CONF, val)
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#define D11CONF_GE(val) CONF_GE(D11CONF, val)
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#define D11CONF_GT(val) CONF_GT(D11CONF, val)
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#define D11CONF_LT(val) CONF_LT(D11CONF, val)
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#define D11CONF_LE(val) CONF_LE(D11CONF, val)
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#define PHYCONF_HAS(val) CONF_HAS(PHYTYPE, val)
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#define PHYCONF_IS(val) CONF_IS(PHYTYPE, val)
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#define NREV_IS(var, val) \
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(NCONF_HAS(val) && (NCONF_IS(val) || ((var) == (val))))
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#define NREV_GE(var, val) \
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(NCONF_GE(val) && (!NCONF_LT(val) || ((var) >= (val))))
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#define NREV_GT(var, val) \
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(NCONF_GT(val) && (!NCONF_LE(val) || ((var) > (val))))
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#define NREV_LT(var, val) \
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(NCONF_LT(val) && (!NCONF_GE(val) || ((var) < (val))))
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#define NREV_LE(var, val) \
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(NCONF_LE(val) && (!NCONF_GT(val) || ((var) <= (val))))
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#define LCNREV_IS(var, val) \
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(LCNCONF_HAS(val) && (LCNCONF_IS(val) || ((var) == (val))))
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#define LCNREV_GE(var, val) \
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(LCNCONF_GE(val) && (!LCNCONF_LT(val) || ((var) >= (val))))
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#define LCNREV_GT(var, val) \
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(LCNCONF_GT(val) && (!LCNCONF_LE(val) || ((var) > (val))))
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#define LCNREV_LT(var, val) \
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(LCNCONF_LT(val) && (!LCNCONF_GE(val) || ((var) < (val))))
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#define LCNREV_LE(var, val) \
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(LCNCONF_LE(val) && (!LCNCONF_GT(val) || ((var) <= (val))))
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#define D11REV_IS(var, val) \
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(D11CONF_HAS(val) && (D11CONF_IS(val) || ((var) == (val))))
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#define D11REV_GE(var, val) \
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(D11CONF_GE(val) && (!D11CONF_LT(val) || ((var) >= (val))))
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#define D11REV_GT(var, val) \
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(D11CONF_GT(val) && (!D11CONF_LE(val) || ((var) > (val))))
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#define D11REV_LT(var, val) \
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(D11CONF_LT(val) && (!D11CONF_GE(val) || ((var) < (val))))
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#define D11REV_LE(var, val) \
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(D11CONF_LE(val) && (!D11CONF_GT(val) || ((var) <= (val))))
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#define PHYTYPE_IS(var, val)\
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(PHYCONF_HAS(val) && (PHYCONF_IS(val) || ((var) == (val))))
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/* Set up PHYTYPE automatically: (depends on PHY_TYPE_X, from d11.h) */
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#define _PHYCONF_N (1 << PHY_TYPE_N)
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#define _PHYCONF_LCN (1 << PHY_TYPE_LCN)
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#define _PHYCONF_SSLPN (1 << PHY_TYPE_SSN)
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#define PHYTYPE (_PHYCONF_N | _PHYCONF_LCN | _PHYCONF_SSLPN)
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/* Utility macro to identify 802.11n (HT) capable PHYs */
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#define PHYTYPE_11N_CAP(phytype) \
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(PHYTYPE_IS(phytype, PHY_TYPE_N) || \
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PHYTYPE_IS(phytype, PHY_TYPE_LCN) || \
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PHYTYPE_IS(phytype, PHY_TYPE_SSN))
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/* Last but not least: shorter wlc-specific var checks */
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#define BRCMS_ISNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_N)
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#define BRCMS_ISLCNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_LCN)
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#define BRCMS_ISSSLPNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_SSN)
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#define BRCMS_PHY_11N_CAP(band) PHYTYPE_11N_CAP((band)->phytype)
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/**********************************************************************
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* ------------- End of Core phy/rev configuration. ----------------- *
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* ********************************************************************
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*/
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#define BCMMSG(dev, fmt, args...) \
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do { \
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if (brcm_msg_level & BRCM_DL_INFO) \
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wiphy_err(dev, "%s: " fmt, __func__, ##args); \
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} while (0)
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#ifdef CONFIG_BCM47XX
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/*
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* bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder
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* transactions. As a fix, a read after write is performed on certain places
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* in the code. Older chips and the newer 5357 family don't require this fix.
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*/
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#define bcma_wflush16(c, o, v) \
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({ bcma_write16(c, o, v); (void)bcma_read16(c, o); })
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#else
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#define bcma_wflush16(c, o, v) bcma_write16(c, o, v)
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#endif /* CONFIG_BCM47XX */
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/* multi-bool data type: set of bools, mbool is true if any is set */
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/* set one bool */
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#define mboolset(mb, bit) ((mb) |= (bit))
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/* clear one bool */
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#define mboolclr(mb, bit) ((mb) &= ~(bit))
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/* true if one bool is set */
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#define mboolisset(mb, bit) (((mb) & (bit)) != 0)
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#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
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#define CEIL(x, y) (((x) + ((y)-1)) / (y))
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/* forward declarations */
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struct wiphy;
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struct ieee80211_sta;
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struct ieee80211_tx_queue_params;
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struct brcms_info;
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struct brcms_c_info;
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struct brcms_hardware;
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struct brcms_band;
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struct dma_pub;
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struct si_pub;
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struct tx_status;
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struct d11rxhdr;
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struct txpwr_limits;
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/* iovar structure */
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struct brcmu_iovar {
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const char *name; /* name for lookup and display */
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u16 varid; /* id for switch */
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u16 flags; /* driver-specific flag bits */
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u16 type; /* base type of argument */
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u16 minlen; /* min length for buffer vars */
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};
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/* brcm_msg_level is a bit vector with defs in defs.h */
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extern u32 brcm_msg_level;
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#endif /* _BRCM_TYPES_H_ */
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