/* SPDX-License-Identifier: ISC */
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/*
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* Copyright (c) 2015-2016 Qualcomm Atheros, Inc.
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*/
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#ifndef _SWAP_H_
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#define _SWAP_H_
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#define ATH10K_SWAP_CODE_SEG_BIN_LEN_MAX (512 * 1024)
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#define ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ 12
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#define ATH10K_SWAP_CODE_SEG_NUM_MAX 16
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/* Currently only one swap segment is supported */
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#define ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED 1
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struct ath10k_fw_file;
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struct ath10k_swap_code_seg_tlv {
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__le32 address;
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__le32 length;
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u8 data[0];
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} __packed;
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struct ath10k_swap_code_seg_tail {
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u8 magic_signature[ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ];
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__le32 bmi_write_addr;
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} __packed;
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union ath10k_swap_code_seg_item {
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struct ath10k_swap_code_seg_tlv tlv;
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struct ath10k_swap_code_seg_tail tail;
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} __packed;
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struct ath10k_swap_code_seg_hw_info {
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/* Swap binary image size */
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__le32 swap_size;
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__le32 num_segs;
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/* Swap data size */
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__le32 size;
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__le32 size_log2;
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__le32 bus_addr[ATH10K_SWAP_CODE_SEG_NUM_MAX];
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__le64 reserved[ATH10K_SWAP_CODE_SEG_NUM_MAX];
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} __packed;
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struct ath10k_swap_code_seg_info {
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struct ath10k_swap_code_seg_hw_info seg_hw_info;
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void *virt_address[ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED];
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u32 target_addr;
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dma_addr_t paddr[ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED];
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};
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int ath10k_swap_code_seg_configure(struct ath10k *ar,
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const struct ath10k_fw_file *fw_file);
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void ath10k_swap_code_seg_release(struct ath10k *ar,
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struct ath10k_fw_file *fw_file);
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int ath10k_swap_code_seg_init(struct ath10k *ar,
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struct ath10k_fw_file *fw_file);
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#endif
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