/* SPDX-License-Identifier: ISC */
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/*
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* Copyright (c) 2018 The Linux Foundation. All rights reserved.
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*/
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#ifndef _SNOC_H_
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#define _SNOC_H_
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#include "hw.h"
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#include "ce.h"
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#include "qmi.h"
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struct ath10k_snoc_drv_priv {
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enum ath10k_hw_rev hw_rev;
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u64 dma_mask;
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u32 msa_size;
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};
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struct snoc_state {
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u32 pipe_cfg_addr;
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u32 svc_to_pipe_map;
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};
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struct ath10k_snoc_pipe {
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struct ath10k_ce_pipe *ce_hdl;
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u8 pipe_num;
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struct ath10k *hif_ce_state;
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size_t buf_sz;
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/* protect ce info */
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spinlock_t pipe_lock;
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struct ath10k_snoc *ar_snoc;
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};
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struct ath10k_snoc_target_info {
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u32 target_version;
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u32 target_type;
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u32 target_revision;
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u32 soc_version;
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};
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struct ath10k_snoc_ce_irq {
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u32 irq_line;
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};
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enum ath10k_snoc_flags {
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ATH10K_SNOC_FLAG_REGISTERED,
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ATH10K_SNOC_FLAG_UNREGISTERING,
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ATH10K_SNOC_FLAG_RECOVERY,
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ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK,
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};
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struct clk_bulk_data;
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struct regulator_bulk_data;
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struct ath10k_snoc {
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struct platform_device *dev;
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struct ath10k *ar;
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unsigned int use_tz;
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struct ath10k_firmware {
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struct device *dev;
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dma_addr_t fw_start_addr;
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struct iommu_domain *iommu_domain;
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size_t mapped_mem_size;
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} fw;
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void __iomem *mem;
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dma_addr_t mem_pa;
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struct ath10k_snoc_target_info target_info;
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size_t mem_len;
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struct ath10k_snoc_pipe pipe_info[CE_COUNT_MAX];
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struct ath10k_snoc_ce_irq ce_irqs[CE_COUNT_MAX];
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struct ath10k_ce ce;
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struct timer_list rx_post_retry;
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struct regulator_bulk_data *vregs;
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size_t num_vregs;
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struct clk_bulk_data *clks;
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size_t num_clks;
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struct ath10k_qmi *qmi;
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unsigned long flags;
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bool xo_cal_supported;
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u32 xo_cal_data;
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DECLARE_BITMAP(pending_ce_irqs, CE_COUNT_MAX);
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};
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static inline struct ath10k_snoc *ath10k_snoc_priv(struct ath10k *ar)
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{
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return (struct ath10k_snoc *)ar->drv_priv;
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}
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int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type);
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void ath10k_snoc_fw_crashed_dump(struct ath10k *ar);
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#endif /* _SNOC_H_ */
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