// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* meth.c -- O2 Builtin 10/100 Ethernet driver
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*
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* Copyright (C) 2001-2003 Ilya Volynets
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*/
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/in.h>
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#include <linux/in6.h>
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#include <linux/device.h> /* struct device, et al */
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#include <linux/netdevice.h> /* struct device, and other headers */
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#include <linux/etherdevice.h> /* eth_type_trans */
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#include <linux/ip.h> /* struct iphdr */
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#include <linux/tcp.h> /* struct tcphdr */
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#include <linux/skbuff.h>
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#include <linux/mii.h> /* MII definitions */
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#include <linux/crc32.h>
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#include <asm/ip32/mace.h>
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#include <asm/ip32/ip32_ints.h>
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#include <asm/io.h>
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#include "meth.h"
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#ifndef MFE_DEBUG
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#define MFE_DEBUG 0
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#endif
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#if MFE_DEBUG>=1
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#define DPRINTK(str,args...) printk(KERN_DEBUG "meth: %s: " str, __func__ , ## args)
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#define MFE_RX_DEBUG 2
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#else
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#define DPRINTK(str,args...)
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#define MFE_RX_DEBUG 0
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#endif
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static const char *meth_str="SGI O2 Fast Ethernet";
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/* The maximum time waited (in jiffies) before assuming a Tx failed. (400ms) */
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#define TX_TIMEOUT (400*HZ/1000)
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static int timeout = TX_TIMEOUT;
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module_param(timeout, int, 0);
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/*
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* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
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* MACE Ethernet uses a 64 element hash table based on the Ethernet CRC.
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*/
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#define METH_MCF_LIMIT 32
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/*
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* This structure is private to each device. It is used to pass
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* packets in and out, so there is place for a packet
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*/
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struct meth_private {
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struct platform_device *pdev;
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/* in-memory copy of MAC Control register */
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u64 mac_ctrl;
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/* in-memory copy of DMA Control register */
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unsigned long dma_ctrl;
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/* address of PHY, used by mdio_* functions, initialized in mdio_probe */
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unsigned long phy_addr;
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tx_packet *tx_ring;
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dma_addr_t tx_ring_dma;
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struct sk_buff *tx_skbs[TX_RING_ENTRIES];
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dma_addr_t tx_skb_dmas[TX_RING_ENTRIES];
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unsigned long tx_read, tx_write, tx_count;
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rx_packet *rx_ring[RX_RING_ENTRIES];
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dma_addr_t rx_ring_dmas[RX_RING_ENTRIES];
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struct sk_buff *rx_skbs[RX_RING_ENTRIES];
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unsigned long rx_write;
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/* Multicast filter. */
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u64 mcast_filter;
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spinlock_t meth_lock;
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};
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static void meth_tx_timeout(struct net_device *dev, unsigned int txqueue);
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static irqreturn_t meth_interrupt(int irq, void *dev_id);
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/* global, initialized in ip32-setup.c */
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char o2meth_eaddr[8]={0,0,0,0,0,0,0,0};
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static inline void load_eaddr(struct net_device *dev)
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{
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int i;
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u64 macaddr;
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DPRINTK("Loading MAC Address: %pM\n", dev->dev_addr);
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macaddr = 0;
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for (i = 0; i < 6; i++)
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macaddr |= (u64)dev->dev_addr[i] << ((5 - i) * 8);
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mace->eth.mac_addr = macaddr;
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}
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/*
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* Waits for BUSY status of mdio bus to clear
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*/
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#define WAIT_FOR_PHY(___rval) \
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while ((___rval = mace->eth.phy_data) & MDIO_BUSY) { \
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udelay(25); \
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}
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/*read phy register, return value read */
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static unsigned long mdio_read(struct meth_private *priv, unsigned long phyreg)
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{
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unsigned long rval;
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WAIT_FOR_PHY(rval);
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mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
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udelay(25);
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mace->eth.phy_trans_go = 1;
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udelay(25);
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WAIT_FOR_PHY(rval);
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return rval & MDIO_DATA_MASK;
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}
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static int mdio_probe(struct meth_private *priv)
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{
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int i;
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unsigned long p2, p3, flags;
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/* check if phy is detected already */
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if(priv->phy_addr>=0&&priv->phy_addr<32)
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return 0;
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spin_lock_irqsave(&priv->meth_lock, flags);
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for (i=0;i<32;++i){
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priv->phy_addr=i;
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p2=mdio_read(priv,2);
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p3=mdio_read(priv,3);
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#if MFE_DEBUG>=2
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switch ((p2<<12)|(p3>>4)){
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case PHY_QS6612X:
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DPRINTK("PHY is QS6612X\n");
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break;
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case PHY_ICS1889:
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DPRINTK("PHY is ICS1889\n");
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break;
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case PHY_ICS1890:
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DPRINTK("PHY is ICS1890\n");
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break;
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case PHY_DP83840:
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DPRINTK("PHY is DP83840\n");
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break;
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}
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#endif
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if(p2!=0xffff&&p2!=0x0000){
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DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4));
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break;
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}
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}
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spin_unlock_irqrestore(&priv->meth_lock, flags);
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if(priv->phy_addr<32) {
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return 0;
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}
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DPRINTK("Oopsie! PHY is not known!\n");
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priv->phy_addr=-1;
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return -ENODEV;
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}
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static void meth_check_link(struct net_device *dev)
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{
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struct meth_private *priv = netdev_priv(dev);
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unsigned long mii_advertising = mdio_read(priv, 4);
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unsigned long mii_partner = mdio_read(priv, 5);
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unsigned long negotiated = mii_advertising & mii_partner;
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unsigned long duplex, speed;
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if (mii_partner == 0xffff)
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return;
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speed = (negotiated & 0x0380) ? METH_100MBIT : 0;
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duplex = ((negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040) ?
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METH_PHY_FDX : 0;
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if ((priv->mac_ctrl & METH_PHY_FDX) ^ duplex) {
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DPRINTK("Setting %s-duplex\n", duplex ? "full" : "half");
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if (duplex)
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priv->mac_ctrl |= METH_PHY_FDX;
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else
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priv->mac_ctrl &= ~METH_PHY_FDX;
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mace->eth.mac_ctrl = priv->mac_ctrl;
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}
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if ((priv->mac_ctrl & METH_100MBIT) ^ speed) {
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DPRINTK("Setting %dMbs mode\n", speed ? 100 : 10);
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if (duplex)
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priv->mac_ctrl |= METH_100MBIT;
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else
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priv->mac_ctrl &= ~METH_100MBIT;
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mace->eth.mac_ctrl = priv->mac_ctrl;
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}
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}
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static int meth_init_tx_ring(struct meth_private *priv)
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{
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/* Init TX ring */
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priv->tx_ring = dma_alloc_coherent(&priv->pdev->dev,
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TX_RING_BUFFER_SIZE, &priv->tx_ring_dma, GFP_ATOMIC);
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if (!priv->tx_ring)
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return -ENOMEM;
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priv->tx_count = priv->tx_read = priv->tx_write = 0;
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mace->eth.tx_ring_base = priv->tx_ring_dma;
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/* Now init skb save area */
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memset(priv->tx_skbs, 0, sizeof(priv->tx_skbs));
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memset(priv->tx_skb_dmas, 0, sizeof(priv->tx_skb_dmas));
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return 0;
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}
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static int meth_init_rx_ring(struct meth_private *priv)
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{
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int i;
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for (i = 0; i < RX_RING_ENTRIES; i++) {
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priv->rx_skbs[i] = alloc_skb(METH_RX_BUFF_SIZE, 0);
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/* 8byte status vector + 3quad padding + 2byte padding,
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* to put data on 64bit aligned boundary */
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skb_reserve(priv->rx_skbs[i],METH_RX_HEAD);
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priv->rx_ring[i]=(rx_packet*)(priv->rx_skbs[i]->head);
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/* I'll need to re-sync it after each RX */
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priv->rx_ring_dmas[i] =
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dma_map_single(&priv->pdev->dev, priv->rx_ring[i],
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METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
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mace->eth.rx_fifo = priv->rx_ring_dmas[i];
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}
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priv->rx_write = 0;
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return 0;
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}
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static void meth_free_tx_ring(struct meth_private *priv)
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{
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int i;
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/* Remove any pending skb */
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for (i = 0; i < TX_RING_ENTRIES; i++) {
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dev_kfree_skb(priv->tx_skbs[i]);
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priv->tx_skbs[i] = NULL;
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}
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dma_free_coherent(&priv->pdev->dev, TX_RING_BUFFER_SIZE, priv->tx_ring,
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priv->tx_ring_dma);
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}
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/* Presumes RX DMA engine is stopped, and RX fifo ring is reset */
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static void meth_free_rx_ring(struct meth_private *priv)
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{
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int i;
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for (i = 0; i < RX_RING_ENTRIES; i++) {
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dma_unmap_single(&priv->pdev->dev, priv->rx_ring_dmas[i],
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METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
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priv->rx_ring[i] = 0;
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priv->rx_ring_dmas[i] = 0;
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kfree_skb(priv->rx_skbs[i]);
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}
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}
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int meth_reset(struct net_device *dev)
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{
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struct meth_private *priv = netdev_priv(dev);
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/* Reset card */
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mace->eth.mac_ctrl = SGI_MAC_RESET;
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udelay(1);
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mace->eth.mac_ctrl = 0;
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udelay(25);
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/* Load ethernet address */
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load_eaddr(dev);
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/* Should load some "errata", but later */
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/* Check for device */
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if (mdio_probe(priv) < 0) {
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DPRINTK("Unable to find PHY\n");
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return -ENODEV;
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}
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/* Initial mode: 10 | Half-duplex | Accept normal packets */
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priv->mac_ctrl = METH_ACCEPT_MCAST | METH_DEFAULT_IPG;
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if (dev->flags & IFF_PROMISC)
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priv->mac_ctrl |= METH_PROMISC;
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mace->eth.mac_ctrl = priv->mac_ctrl;
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/* Autonegotiate speed and duplex mode */
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meth_check_link(dev);
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/* Now set dma control, but don't enable DMA, yet */
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priv->dma_ctrl = (4 << METH_RX_OFFSET_SHIFT) |
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(RX_RING_ENTRIES << METH_RX_DEPTH_SHIFT);
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mace->eth.dma_ctrl = priv->dma_ctrl;
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return 0;
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}
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/*============End Helper Routines=====================*/
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/*
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* Open and close
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*/
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static int meth_open(struct net_device *dev)
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{
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struct meth_private *priv = netdev_priv(dev);
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int ret;
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priv->phy_addr = -1; /* No PHY is known yet... */
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/* Initialize the hardware */
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ret = meth_reset(dev);
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if (ret < 0)
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return ret;
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/* Allocate the ring buffers */
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ret = meth_init_tx_ring(priv);
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if (ret < 0)
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return ret;
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ret = meth_init_rx_ring(priv);
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if (ret < 0)
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goto out_free_tx_ring;
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ret = request_irq(dev->irq, meth_interrupt, 0, meth_str, dev);
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if (ret) {
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printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
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goto out_free_rx_ring;
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}
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/* Start DMA */
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priv->dma_ctrl |= METH_DMA_TX_EN | /*METH_DMA_TX_INT_EN |*/
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METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
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mace->eth.dma_ctrl = priv->dma_ctrl;
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DPRINTK("About to start queue\n");
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netif_start_queue(dev);
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return 0;
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out_free_rx_ring:
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meth_free_rx_ring(priv);
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out_free_tx_ring:
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meth_free_tx_ring(priv);
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return ret;
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}
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static int meth_release(struct net_device *dev)
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{
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struct meth_private *priv = netdev_priv(dev);
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DPRINTK("Stopping queue\n");
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netif_stop_queue(dev); /* can't transmit any more */
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/* shut down DMA */
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priv->dma_ctrl &= ~(METH_DMA_TX_EN | METH_DMA_TX_INT_EN |
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METH_DMA_RX_EN | METH_DMA_RX_INT_EN);
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mace->eth.dma_ctrl = priv->dma_ctrl;
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free_irq(dev->irq, dev);
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meth_free_tx_ring(priv);
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meth_free_rx_ring(priv);
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return 0;
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}
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/*
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* Receive a packet: retrieve, encapsulate and pass over to upper levels
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*/
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static void meth_rx(struct net_device* dev, unsigned long int_status)
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{
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struct sk_buff *skb;
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unsigned long status, flags;
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struct meth_private *priv = netdev_priv(dev);
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unsigned long fifo_rptr = (int_status & METH_INT_RX_RPTR_MASK) >> 8;
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spin_lock_irqsave(&priv->meth_lock, flags);
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priv->dma_ctrl &= ~METH_DMA_RX_INT_EN;
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mace->eth.dma_ctrl = priv->dma_ctrl;
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spin_unlock_irqrestore(&priv->meth_lock, flags);
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if (int_status & METH_INT_RX_UNDERFLOW) {
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fifo_rptr = (fifo_rptr - 1) & 0x0f;
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}
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while (priv->rx_write != fifo_rptr) {
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dma_unmap_single(&priv->pdev->dev,
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priv->rx_ring_dmas[priv->rx_write],
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METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
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status = priv->rx_ring[priv->rx_write]->status.raw;
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#if MFE_DEBUG
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if (!(status & METH_RX_ST_VALID)) {
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DPRINTK("Not received? status=%016lx\n",status);
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}
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#endif
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if ((!(status & METH_RX_STATUS_ERRORS)) && (status & METH_RX_ST_VALID)) {
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int len = (status & 0xffff) - 4; /* omit CRC */
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/* length sanity check */
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if (len < 60 || len > 1518) {
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printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2Lx.\n",
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dev->name, priv->rx_write,
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priv->rx_ring[priv->rx_write]->status.raw);
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dev->stats.rx_errors++;
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dev->stats.rx_length_errors++;
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skb = priv->rx_skbs[priv->rx_write];
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} else {
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skb = alloc_skb(METH_RX_BUFF_SIZE, GFP_ATOMIC);
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if (!skb) {
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/* Ouch! No memory! Drop packet on the floor */
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DPRINTK("No mem: dropping packet\n");
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dev->stats.rx_dropped++;
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skb = priv->rx_skbs[priv->rx_write];
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} else {
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struct sk_buff *skb_c = priv->rx_skbs[priv->rx_write];
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/* 8byte status vector + 3quad padding + 2byte padding,
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* to put data on 64bit aligned boundary */
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skb_reserve(skb, METH_RX_HEAD);
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/* Write metadata, and then pass to the receive level */
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skb_put(skb_c, len);
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priv->rx_skbs[priv->rx_write] = skb;
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skb_c->protocol = eth_type_trans(skb_c, dev);
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dev->stats.rx_packets++;
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dev->stats.rx_bytes += len;
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netif_rx(skb_c);
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}
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}
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} else {
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dev->stats.rx_errors++;
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skb=priv->rx_skbs[priv->rx_write];
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#if MFE_DEBUG>0
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printk(KERN_WARNING "meth: RX error: status=0x%016lx\n",status);
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if(status&METH_RX_ST_RCV_CODE_VIOLATION)
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printk(KERN_WARNING "Receive Code Violation\n");
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if(status&METH_RX_ST_CRC_ERR)
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printk(KERN_WARNING "CRC error\n");
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if(status&METH_RX_ST_INV_PREAMBLE_CTX)
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printk(KERN_WARNING "Invalid Preamble Context\n");
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if(status&METH_RX_ST_LONG_EVT_SEEN)
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printk(KERN_WARNING "Long Event Seen...\n");
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if(status&METH_RX_ST_BAD_PACKET)
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printk(KERN_WARNING "Bad Packet\n");
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if(status&METH_RX_ST_CARRIER_EVT_SEEN)
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printk(KERN_WARNING "Carrier Event Seen\n");
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#endif
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}
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priv->rx_ring[priv->rx_write] = (rx_packet*)skb->head;
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priv->rx_ring[priv->rx_write]->status.raw = 0;
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priv->rx_ring_dmas[priv->rx_write] =
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dma_map_single(&priv->pdev->dev,
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priv->rx_ring[priv->rx_write],
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METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
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mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
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ADVANCE_RX_PTR(priv->rx_write);
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}
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spin_lock_irqsave(&priv->meth_lock, flags);
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/* In case there was underflow, and Rx DMA was disabled */
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priv->dma_ctrl |= METH_DMA_RX_INT_EN | METH_DMA_RX_EN;
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mace->eth.dma_ctrl = priv->dma_ctrl;
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mace->eth.int_stat = METH_INT_RX_THRESHOLD;
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spin_unlock_irqrestore(&priv->meth_lock, flags);
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}
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static int meth_tx_full(struct net_device *dev)
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{
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struct meth_private *priv = netdev_priv(dev);
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return priv->tx_count >= TX_RING_ENTRIES - 1;
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}
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static void meth_tx_cleanup(struct net_device* dev, unsigned long int_status)
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{
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struct meth_private *priv = netdev_priv(dev);
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unsigned long status, flags;
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struct sk_buff *skb;
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unsigned long rptr = (int_status&TX_INFO_RPTR) >> 16;
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spin_lock_irqsave(&priv->meth_lock, flags);
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/* Stop DMA notification */
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priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
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mace->eth.dma_ctrl = priv->dma_ctrl;
|
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while (priv->tx_read != rptr) {
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skb = priv->tx_skbs[priv->tx_read];
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status = priv->tx_ring[priv->tx_read].header.raw;
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#if MFE_DEBUG>=1
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if (priv->tx_read == priv->tx_write)
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DPRINTK("Auchi! tx_read=%d,tx_write=%d,rptr=%d?\n", priv->tx_read, priv->tx_write,rptr);
|
#endif
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if (status & METH_TX_ST_DONE) {
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if (status & METH_TX_ST_SUCCESS){
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dev->stats.tx_packets++;
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dev->stats.tx_bytes += skb->len;
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} else {
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dev->stats.tx_errors++;
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#if MFE_DEBUG>=1
|
DPRINTK("TX error: status=%016lx <",status);
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if(status & METH_TX_ST_SUCCESS)
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printk(" SUCCESS");
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if(status & METH_TX_ST_TOOLONG)
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printk(" TOOLONG");
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if(status & METH_TX_ST_UNDERRUN)
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printk(" UNDERRUN");
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if(status & METH_TX_ST_EXCCOLL)
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printk(" EXCCOLL");
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if(status & METH_TX_ST_DEFER)
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printk(" DEFER");
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if(status & METH_TX_ST_LATECOLL)
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printk(" LATECOLL");
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printk(" >\n");
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#endif
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}
|
} else {
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DPRINTK("RPTR points us here, but packet not done?\n");
|
break;
|
}
|
dev_consume_skb_irq(skb);
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priv->tx_skbs[priv->tx_read] = NULL;
|
priv->tx_ring[priv->tx_read].header.raw = 0;
|
priv->tx_read = (priv->tx_read+1)&(TX_RING_ENTRIES-1);
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priv->tx_count--;
|
}
|
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/* wake up queue if it was stopped */
|
if (netif_queue_stopped(dev) && !meth_tx_full(dev)) {
|
netif_wake_queue(dev);
|
}
|
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mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
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spin_unlock_irqrestore(&priv->meth_lock, flags);
|
}
|
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static void meth_error(struct net_device* dev, unsigned status)
|
{
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struct meth_private *priv = netdev_priv(dev);
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unsigned long flags;
|
|
printk(KERN_WARNING "meth: error status: 0x%08x\n",status);
|
/* check for errors too... */
|
if (status & (METH_INT_TX_LINK_FAIL))
|
printk(KERN_WARNING "meth: link failure\n");
|
/* Should I do full reset in this case? */
|
if (status & (METH_INT_MEM_ERROR))
|
printk(KERN_WARNING "meth: memory error\n");
|
if (status & (METH_INT_TX_ABORT))
|
printk(KERN_WARNING "meth: aborted\n");
|
if (status & (METH_INT_RX_OVERFLOW))
|
printk(KERN_WARNING "meth: Rx overflow\n");
|
if (status & (METH_INT_RX_UNDERFLOW)) {
|
printk(KERN_WARNING "meth: Rx underflow\n");
|
spin_lock_irqsave(&priv->meth_lock, flags);
|
mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
|
/* more underflow interrupts will be delivered,
|
* effectively throwing us into an infinite loop.
|
* Thus I stop processing Rx in this case. */
|
priv->dma_ctrl &= ~METH_DMA_RX_EN;
|
mace->eth.dma_ctrl = priv->dma_ctrl;
|
DPRINTK("Disabled meth Rx DMA temporarily\n");
|
spin_unlock_irqrestore(&priv->meth_lock, flags);
|
}
|
mace->eth.int_stat = METH_INT_ERROR;
|
}
|
|
/*
|
* The typical interrupt entry point
|
*/
|
static irqreturn_t meth_interrupt(int irq, void *dev_id)
|
{
|
struct net_device *dev = (struct net_device *)dev_id;
|
struct meth_private *priv = netdev_priv(dev);
|
unsigned long status;
|
|
status = mace->eth.int_stat;
|
while (status & 0xff) {
|
/* First handle errors - if we get Rx underflow,
|
* Rx DMA will be disabled, and Rx handler will reenable
|
* it. I don't think it's possible to get Rx underflow,
|
* without getting Rx interrupt */
|
if (status & METH_INT_ERROR) {
|
meth_error(dev, status);
|
}
|
if (status & (METH_INT_TX_EMPTY | METH_INT_TX_PKT)) {
|
/* a transmission is over: free the skb */
|
meth_tx_cleanup(dev, status);
|
}
|
if (status & METH_INT_RX_THRESHOLD) {
|
if (!(priv->dma_ctrl & METH_DMA_RX_INT_EN))
|
break;
|
/* send it to meth_rx for handling */
|
meth_rx(dev, status);
|
}
|
status = mace->eth.int_stat;
|
}
|
|
return IRQ_HANDLED;
|
}
|
|
/*
|
* Transmits packets that fit into TX descriptor (are <=120B)
|
*/
|
static void meth_tx_short_prepare(struct meth_private *priv,
|
struct sk_buff *skb)
|
{
|
tx_packet *desc = &priv->tx_ring[priv->tx_write];
|
int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
|
|
desc->header.raw = METH_TX_CMD_INT_EN | (len-1) | ((128-len) << 16);
|
/* maybe I should set whole thing to 0 first... */
|
skb_copy_from_linear_data(skb, desc->data.dt + (120 - len), skb->len);
|
if (skb->len < len)
|
memset(desc->data.dt + 120 - len + skb->len, 0, len-skb->len);
|
}
|
#define TX_CATBUF1 BIT(25)
|
static void meth_tx_1page_prepare(struct meth_private *priv,
|
struct sk_buff *skb)
|
{
|
tx_packet *desc = &priv->tx_ring[priv->tx_write];
|
void *buffer_data = (void *)(((unsigned long)skb->data + 7) & ~7);
|
int unaligned_len = (int)((unsigned long)buffer_data - (unsigned long)skb->data);
|
int buffer_len = skb->len - unaligned_len;
|
dma_addr_t catbuf;
|
|
desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | (skb->len - 1);
|
|
/* unaligned part */
|
if (unaligned_len) {
|
skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
|
unaligned_len);
|
desc->header.raw |= (128 - unaligned_len) << 16;
|
}
|
|
/* first page */
|
catbuf = dma_map_single(&priv->pdev->dev, buffer_data, buffer_len,
|
DMA_TO_DEVICE);
|
desc->data.cat_buf[0].form.start_addr = catbuf >> 3;
|
desc->data.cat_buf[0].form.len = buffer_len - 1;
|
}
|
#define TX_CATBUF2 BIT(26)
|
static void meth_tx_2page_prepare(struct meth_private *priv,
|
struct sk_buff *skb)
|
{
|
tx_packet *desc = &priv->tx_ring[priv->tx_write];
|
void *buffer1_data = (void *)(((unsigned long)skb->data + 7) & ~7);
|
void *buffer2_data = (void *)PAGE_ALIGN((unsigned long)skb->data);
|
int unaligned_len = (int)((unsigned long)buffer1_data - (unsigned long)skb->data);
|
int buffer1_len = (int)((unsigned long)buffer2_data - (unsigned long)buffer1_data);
|
int buffer2_len = skb->len - buffer1_len - unaligned_len;
|
dma_addr_t catbuf1, catbuf2;
|
|
desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | TX_CATBUF2| (skb->len - 1);
|
/* unaligned part */
|
if (unaligned_len){
|
skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
|
unaligned_len);
|
desc->header.raw |= (128 - unaligned_len) << 16;
|
}
|
|
/* first page */
|
catbuf1 = dma_map_single(&priv->pdev->dev, buffer1_data, buffer1_len,
|
DMA_TO_DEVICE);
|
desc->data.cat_buf[0].form.start_addr = catbuf1 >> 3;
|
desc->data.cat_buf[0].form.len = buffer1_len - 1;
|
/* second page */
|
catbuf2 = dma_map_single(&priv->pdev->dev, buffer2_data, buffer2_len,
|
DMA_TO_DEVICE);
|
desc->data.cat_buf[1].form.start_addr = catbuf2 >> 3;
|
desc->data.cat_buf[1].form.len = buffer2_len - 1;
|
}
|
|
static void meth_add_to_tx_ring(struct meth_private *priv, struct sk_buff *skb)
|
{
|
/* Remember the skb, so we can free it at interrupt time */
|
priv->tx_skbs[priv->tx_write] = skb;
|
if (skb->len <= 120) {
|
/* Whole packet fits into descriptor */
|
meth_tx_short_prepare(priv, skb);
|
} else if (PAGE_ALIGN((unsigned long)skb->data) !=
|
PAGE_ALIGN((unsigned long)skb->data + skb->len - 1)) {
|
/* Packet crosses page boundary */
|
meth_tx_2page_prepare(priv, skb);
|
} else {
|
/* Packet is in one page */
|
meth_tx_1page_prepare(priv, skb);
|
}
|
priv->tx_write = (priv->tx_write + 1) & (TX_RING_ENTRIES - 1);
|
mace->eth.tx_info = priv->tx_write;
|
priv->tx_count++;
|
}
|
|
/*
|
* Transmit a packet (called by the kernel)
|
*/
|
static netdev_tx_t meth_tx(struct sk_buff *skb, struct net_device *dev)
|
{
|
struct meth_private *priv = netdev_priv(dev);
|
unsigned long flags;
|
|
spin_lock_irqsave(&priv->meth_lock, flags);
|
/* Stop DMA notification */
|
priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
|
mace->eth.dma_ctrl = priv->dma_ctrl;
|
|
meth_add_to_tx_ring(priv, skb);
|
netif_trans_update(dev); /* save the timestamp */
|
|
/* If TX ring is full, tell the upper layer to stop sending packets */
|
if (meth_tx_full(dev)) {
|
printk(KERN_DEBUG "TX full: stopping\n");
|
netif_stop_queue(dev);
|
}
|
|
/* Restart DMA notification */
|
priv->dma_ctrl |= METH_DMA_TX_INT_EN;
|
mace->eth.dma_ctrl = priv->dma_ctrl;
|
|
spin_unlock_irqrestore(&priv->meth_lock, flags);
|
|
return NETDEV_TX_OK;
|
}
|
|
/*
|
* Deal with a transmit timeout.
|
*/
|
static void meth_tx_timeout(struct net_device *dev, unsigned int txqueue)
|
{
|
struct meth_private *priv = netdev_priv(dev);
|
unsigned long flags;
|
|
printk(KERN_WARNING "%s: transmit timed out\n", dev->name);
|
|
/* Protect against concurrent rx interrupts */
|
spin_lock_irqsave(&priv->meth_lock,flags);
|
|
/* Try to reset the interface. */
|
meth_reset(dev);
|
|
dev->stats.tx_errors++;
|
|
/* Clear all rings */
|
meth_free_tx_ring(priv);
|
meth_free_rx_ring(priv);
|
meth_init_tx_ring(priv);
|
meth_init_rx_ring(priv);
|
|
/* Restart dma */
|
priv->dma_ctrl |= METH_DMA_TX_EN | METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
|
mace->eth.dma_ctrl = priv->dma_ctrl;
|
|
/* Enable interrupt */
|
spin_unlock_irqrestore(&priv->meth_lock, flags);
|
|
netif_trans_update(dev); /* prevent tx timeout */
|
netif_wake_queue(dev);
|
}
|
|
/*
|
* Ioctl commands
|
*/
|
static int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
|
{
|
/* XXX Not yet implemented */
|
switch(cmd) {
|
case SIOCGMIIPHY:
|
case SIOCGMIIREG:
|
case SIOCSMIIREG:
|
default:
|
return -EOPNOTSUPP;
|
}
|
}
|
|
static void meth_set_rx_mode(struct net_device *dev)
|
{
|
struct meth_private *priv = netdev_priv(dev);
|
unsigned long flags;
|
|
netif_stop_queue(dev);
|
spin_lock_irqsave(&priv->meth_lock, flags);
|
priv->mac_ctrl &= ~METH_PROMISC;
|
|
if (dev->flags & IFF_PROMISC) {
|
priv->mac_ctrl |= METH_PROMISC;
|
priv->mcast_filter = 0xffffffffffffffffUL;
|
} else if ((netdev_mc_count(dev) > METH_MCF_LIMIT) ||
|
(dev->flags & IFF_ALLMULTI)) {
|
priv->mac_ctrl |= METH_ACCEPT_AMCAST;
|
priv->mcast_filter = 0xffffffffffffffffUL;
|
} else {
|
struct netdev_hw_addr *ha;
|
priv->mac_ctrl |= METH_ACCEPT_MCAST;
|
|
netdev_for_each_mc_addr(ha, dev)
|
set_bit((ether_crc(ETH_ALEN, ha->addr) >> 26),
|
(volatile unsigned long *)&priv->mcast_filter);
|
}
|
|
/* Write the changes to the chip registers. */
|
mace->eth.mac_ctrl = priv->mac_ctrl;
|
mace->eth.mcast_filter = priv->mcast_filter;
|
|
/* Done! */
|
spin_unlock_irqrestore(&priv->meth_lock, flags);
|
netif_wake_queue(dev);
|
}
|
|
static const struct net_device_ops meth_netdev_ops = {
|
.ndo_open = meth_open,
|
.ndo_stop = meth_release,
|
.ndo_start_xmit = meth_tx,
|
.ndo_do_ioctl = meth_ioctl,
|
.ndo_tx_timeout = meth_tx_timeout,
|
.ndo_validate_addr = eth_validate_addr,
|
.ndo_set_mac_address = eth_mac_addr,
|
.ndo_set_rx_mode = meth_set_rx_mode,
|
};
|
|
/*
|
* The init function.
|
*/
|
static int meth_probe(struct platform_device *pdev)
|
{
|
struct net_device *dev;
|
struct meth_private *priv;
|
int err;
|
|
dev = alloc_etherdev(sizeof(struct meth_private));
|
if (!dev)
|
return -ENOMEM;
|
|
dev->netdev_ops = &meth_netdev_ops;
|
dev->watchdog_timeo = timeout;
|
dev->irq = MACE_ETHERNET_IRQ;
|
dev->base_addr = (unsigned long)&mace->eth;
|
memcpy(dev->dev_addr, o2meth_eaddr, ETH_ALEN);
|
|
priv = netdev_priv(dev);
|
priv->pdev = pdev;
|
spin_lock_init(&priv->meth_lock);
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
err = register_netdev(dev);
|
if (err) {
|
free_netdev(dev);
|
return err;
|
}
|
|
printk(KERN_INFO "%s: SGI MACE Ethernet rev. %d\n",
|
dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));
|
return 0;
|
}
|
|
static int meth_remove(struct platform_device *pdev)
|
{
|
struct net_device *dev = platform_get_drvdata(pdev);
|
|
unregister_netdev(dev);
|
free_netdev(dev);
|
|
return 0;
|
}
|
|
static struct platform_driver meth_driver = {
|
.probe = meth_probe,
|
.remove = meth_remove,
|
.driver = {
|
.name = "meth",
|
}
|
};
|
|
module_platform_driver(meth_driver);
|
|
MODULE_AUTHOR("Ilya Volynets <ilya@theIlya.com>");
|
MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver");
|
MODULE_LICENSE("GPL");
|
MODULE_ALIAS("platform:meth");
|
