// SPDX-License-Identifier: GPL-2.0-only
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/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2018 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include "net_driver.h"
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#include "efx.h"
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#include "nic_common.h"
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#include "tx_common.h"
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static unsigned int efx_tx_cb_page_count(struct efx_tx_queue *tx_queue)
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{
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return DIV_ROUND_UP(tx_queue->ptr_mask + 1,
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PAGE_SIZE >> EFX_TX_CB_ORDER);
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}
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int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
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{
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struct efx_nic *efx = tx_queue->efx;
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unsigned int entries;
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int rc;
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/* Create the smallest power-of-two aligned ring */
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entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
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EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
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tx_queue->ptr_mask = entries - 1;
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netif_dbg(efx, probe, efx->net_dev,
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"creating TX queue %d size %#x mask %#x\n",
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tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
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/* Allocate software ring */
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tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
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GFP_KERNEL);
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if (!tx_queue->buffer)
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return -ENOMEM;
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tx_queue->cb_page = kcalloc(efx_tx_cb_page_count(tx_queue),
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sizeof(tx_queue->cb_page[0]), GFP_KERNEL);
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if (!tx_queue->cb_page) {
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rc = -ENOMEM;
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goto fail1;
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}
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/* Allocate hardware ring, determine TXQ type */
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rc = efx_nic_probe_tx(tx_queue);
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if (rc)
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goto fail2;
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tx_queue->channel->tx_queue_by_type[tx_queue->type] = tx_queue;
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return 0;
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fail2:
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kfree(tx_queue->cb_page);
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tx_queue->cb_page = NULL;
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fail1:
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kfree(tx_queue->buffer);
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tx_queue->buffer = NULL;
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return rc;
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}
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void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
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{
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struct efx_nic *efx = tx_queue->efx;
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netif_dbg(efx, drv, efx->net_dev,
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"initialising TX queue %d\n", tx_queue->queue);
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tx_queue->insert_count = 0;
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tx_queue->notify_count = 0;
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tx_queue->write_count = 0;
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tx_queue->packet_write_count = 0;
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tx_queue->old_write_count = 0;
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tx_queue->read_count = 0;
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tx_queue->old_read_count = 0;
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tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
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tx_queue->xmit_pending = false;
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tx_queue->timestamping = (efx_ptp_use_mac_tx_timestamps(efx) &&
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tx_queue->channel == efx_ptp_channel(efx));
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tx_queue->completed_timestamp_major = 0;
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tx_queue->completed_timestamp_minor = 0;
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tx_queue->xdp_tx = efx_channel_is_xdp_tx(tx_queue->channel);
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tx_queue->tso_version = 0;
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/* Set up TX descriptor ring */
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efx_nic_init_tx(tx_queue);
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tx_queue->initialised = true;
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}
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void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
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{
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struct efx_tx_buffer *buffer;
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netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
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"shutting down TX queue %d\n", tx_queue->queue);
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if (!tx_queue->buffer)
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return;
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/* Free any buffers left in the ring */
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while (tx_queue->read_count != tx_queue->write_count) {
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unsigned int pkts_compl = 0, bytes_compl = 0;
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buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
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efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
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++tx_queue->read_count;
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}
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tx_queue->xmit_pending = false;
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netdev_tx_reset_queue(tx_queue->core_txq);
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}
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void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
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{
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int i;
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if (!tx_queue->buffer)
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return;
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netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
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"destroying TX queue %d\n", tx_queue->queue);
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efx_nic_remove_tx(tx_queue);
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if (tx_queue->cb_page) {
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for (i = 0; i < efx_tx_cb_page_count(tx_queue); i++)
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efx_nic_free_buffer(tx_queue->efx,
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&tx_queue->cb_page[i]);
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kfree(tx_queue->cb_page);
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tx_queue->cb_page = NULL;
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}
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kfree(tx_queue->buffer);
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tx_queue->buffer = NULL;
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tx_queue->channel->tx_queue_by_type[tx_queue->type] = NULL;
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}
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void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
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struct efx_tx_buffer *buffer,
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unsigned int *pkts_compl,
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unsigned int *bytes_compl)
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{
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if (buffer->unmap_len) {
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struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
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dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
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if (buffer->flags & EFX_TX_BUF_MAP_SINGLE)
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dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
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DMA_TO_DEVICE);
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else
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dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
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DMA_TO_DEVICE);
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buffer->unmap_len = 0;
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}
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if (buffer->flags & EFX_TX_BUF_SKB) {
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struct sk_buff *skb = (struct sk_buff *)buffer->skb;
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EFX_WARN_ON_PARANOID(!pkts_compl || !bytes_compl);
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(*pkts_compl)++;
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(*bytes_compl) += skb->len;
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if (tx_queue->timestamping &&
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(tx_queue->completed_timestamp_major ||
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tx_queue->completed_timestamp_minor)) {
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struct skb_shared_hwtstamps hwtstamp;
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hwtstamp.hwtstamp =
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efx_ptp_nic_to_kernel_time(tx_queue);
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skb_tstamp_tx(skb, &hwtstamp);
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tx_queue->completed_timestamp_major = 0;
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tx_queue->completed_timestamp_minor = 0;
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}
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dev_consume_skb_any((struct sk_buff *)buffer->skb);
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netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
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"TX queue %d transmission id %x complete\n",
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tx_queue->queue, tx_queue->read_count);
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} else if (buffer->flags & EFX_TX_BUF_XDP) {
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xdp_return_frame_rx_napi(buffer->xdpf);
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}
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buffer->len = 0;
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buffer->flags = 0;
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}
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/* Remove packets from the TX queue
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*
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* This removes packets from the TX queue, up to and including the
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* specified index.
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*/
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static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
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unsigned int index,
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unsigned int *pkts_compl,
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unsigned int *bytes_compl)
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{
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struct efx_nic *efx = tx_queue->efx;
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unsigned int stop_index, read_ptr;
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stop_index = (index + 1) & tx_queue->ptr_mask;
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read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
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while (read_ptr != stop_index) {
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struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
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if (!efx_tx_buffer_in_use(buffer)) {
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netif_err(efx, tx_err, efx->net_dev,
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"TX queue %d spurious TX completion id %d\n",
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tx_queue->queue, read_ptr);
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efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
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return;
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}
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efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl);
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++tx_queue->read_count;
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read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
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}
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}
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void efx_xmit_done_check_empty(struct efx_tx_queue *tx_queue)
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{
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if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
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tx_queue->old_write_count = READ_ONCE(tx_queue->write_count);
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if (tx_queue->read_count == tx_queue->old_write_count) {
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/* Ensure that read_count is flushed. */
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smp_mb();
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tx_queue->empty_read_count =
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tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
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}
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}
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}
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void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
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{
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unsigned int fill_level, pkts_compl = 0, bytes_compl = 0;
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struct efx_nic *efx = tx_queue->efx;
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EFX_WARN_ON_ONCE_PARANOID(index > tx_queue->ptr_mask);
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efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl);
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tx_queue->pkts_compl += pkts_compl;
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tx_queue->bytes_compl += bytes_compl;
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if (pkts_compl > 1)
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++tx_queue->merge_events;
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/* See if we need to restart the netif queue. This memory
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* barrier ensures that we write read_count (inside
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* efx_dequeue_buffers()) before reading the queue status.
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*/
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smp_mb();
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if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) &&
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likely(efx->port_enabled) &&
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likely(netif_device_present(efx->net_dev))) {
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fill_level = efx_channel_tx_fill_level(tx_queue->channel);
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if (fill_level <= efx->txq_wake_thresh)
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netif_tx_wake_queue(tx_queue->core_txq);
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}
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efx_xmit_done_check_empty(tx_queue);
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}
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/* Remove buffers put into a tx_queue for the current packet.
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* None of the buffers must have an skb attached.
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*/
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void efx_enqueue_unwind(struct efx_tx_queue *tx_queue,
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unsigned int insert_count)
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{
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struct efx_tx_buffer *buffer;
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unsigned int bytes_compl = 0;
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unsigned int pkts_compl = 0;
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/* Work backwards until we hit the original insert pointer value */
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while (tx_queue->insert_count != insert_count) {
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--tx_queue->insert_count;
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buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
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efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
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}
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}
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struct efx_tx_buffer *efx_tx_map_chunk(struct efx_tx_queue *tx_queue,
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dma_addr_t dma_addr, size_t len)
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{
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const struct efx_nic_type *nic_type = tx_queue->efx->type;
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struct efx_tx_buffer *buffer;
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unsigned int dma_len;
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/* Map the fragment taking account of NIC-dependent DMA limits. */
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do {
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buffer = efx_tx_queue_get_insert_buffer(tx_queue);
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if (nic_type->tx_limit_len)
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dma_len = nic_type->tx_limit_len(tx_queue, dma_addr, len);
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else
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dma_len = len;
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buffer->len = dma_len;
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buffer->dma_addr = dma_addr;
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buffer->flags = EFX_TX_BUF_CONT;
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len -= dma_len;
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dma_addr += dma_len;
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++tx_queue->insert_count;
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} while (len);
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return buffer;
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}
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int efx_tx_tso_header_length(struct sk_buff *skb)
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{
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size_t header_len;
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if (skb->encapsulation)
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header_len = skb_inner_transport_header(skb) -
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skb->data +
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(inner_tcp_hdr(skb)->doff << 2u);
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else
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header_len = skb_transport_header(skb) - skb->data +
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(tcp_hdr(skb)->doff << 2u);
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return header_len;
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}
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/* Map all data from an SKB for DMA and create descriptors on the queue. */
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int efx_tx_map_data(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
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unsigned int segment_count)
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{
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struct efx_nic *efx = tx_queue->efx;
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struct device *dma_dev = &efx->pci_dev->dev;
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unsigned int frag_index, nr_frags;
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dma_addr_t dma_addr, unmap_addr;
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unsigned short dma_flags;
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size_t len, unmap_len;
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nr_frags = skb_shinfo(skb)->nr_frags;
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frag_index = 0;
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/* Map header data. */
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len = skb_headlen(skb);
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dma_addr = dma_map_single(dma_dev, skb->data, len, DMA_TO_DEVICE);
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dma_flags = EFX_TX_BUF_MAP_SINGLE;
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unmap_len = len;
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unmap_addr = dma_addr;
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if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
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return -EIO;
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if (segment_count) {
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/* For TSO we need to put the header in to a separate
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* descriptor. Map this separately if necessary.
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*/
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size_t header_len = efx_tx_tso_header_length(skb);
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if (header_len != len) {
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tx_queue->tso_long_headers++;
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efx_tx_map_chunk(tx_queue, dma_addr, header_len);
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len -= header_len;
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dma_addr += header_len;
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}
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}
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/* Add descriptors for each fragment. */
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do {
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struct efx_tx_buffer *buffer;
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skb_frag_t *fragment;
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buffer = efx_tx_map_chunk(tx_queue, dma_addr, len);
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/* The final descriptor for a fragment is responsible for
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* unmapping the whole fragment.
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*/
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buffer->flags = EFX_TX_BUF_CONT | dma_flags;
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buffer->unmap_len = unmap_len;
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buffer->dma_offset = buffer->dma_addr - unmap_addr;
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if (frag_index >= nr_frags) {
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/* Store SKB details with the final buffer for
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* the completion.
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*/
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buffer->skb = skb;
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buffer->flags = EFX_TX_BUF_SKB | dma_flags;
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return 0;
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}
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/* Move on to the next fragment. */
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fragment = &skb_shinfo(skb)->frags[frag_index++];
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len = skb_frag_size(fragment);
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dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len,
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DMA_TO_DEVICE);
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dma_flags = 0;
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unmap_len = len;
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unmap_addr = dma_addr;
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if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
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return -EIO;
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} while (1);
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}
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unsigned int efx_tx_max_skb_descs(struct efx_nic *efx)
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{
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/* Header and payload descriptor for each output segment, plus
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* one for every input fragment boundary within a segment
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*/
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unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
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/* Possibly one more per segment for option descriptors */
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if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
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max_descs += EFX_TSO_MAX_SEGS;
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/* Possibly more for PCIe page boundaries within input fragments */
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if (PAGE_SIZE > EFX_PAGE_SIZE)
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max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
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DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE));
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return max_descs;
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}
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/*
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* Fallback to software TSO.
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*
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* This is used if we are unable to send a GSO packet through hardware TSO.
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* This should only ever happen due to per-queue restrictions - unsupported
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* packets should first be filtered by the feature flags.
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*
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* Returns 0 on success, error code otherwise.
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*/
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int efx_tx_tso_fallback(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
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{
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struct sk_buff *segments, *next;
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segments = skb_gso_segment(skb, 0);
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if (IS_ERR(segments))
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return PTR_ERR(segments);
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dev_consume_skb_any(skb);
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skb_list_walk_safe(segments, skb, next) {
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skb_mark_not_on_list(skb);
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efx_enqueue_skb(tx_queue, skb);
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}
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return 0;
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}
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