// SPDX-License-Identifier: GPL-2.0-only
|
/****************************************************************************
|
* Driver for Solarflare network controllers and boards
|
* Copyright 2005-2006 Fen Systems Ltd.
|
* Copyright 2005-2013 Solarflare Communications Inc.
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*/
|
|
#include <linux/pci.h>
|
#include <linux/tcp.h>
|
#include <linux/ip.h>
|
#include <linux/in.h>
|
#include <linux/ipv6.h>
|
#include <linux/slab.h>
|
#include <net/ipv6.h>
|
#include <linux/if_ether.h>
|
#include <linux/highmem.h>
|
#include <linux/cache.h>
|
#include "net_driver.h"
|
#include "efx.h"
|
#include "io.h"
|
#include "nic.h"
|
#include "tx.h"
|
#include "tx_common.h"
|
#include "workarounds.h"
|
#include "ef10_regs.h"
|
|
#ifdef EFX_USE_PIO
|
|
#define EFX_PIOBUF_SIZE_DEF ALIGN(256, L1_CACHE_BYTES)
|
unsigned int efx_piobuf_size __read_mostly = EFX_PIOBUF_SIZE_DEF;
|
|
#endif /* EFX_USE_PIO */
|
|
static inline u8 *efx_tx_get_copy_buffer(struct efx_tx_queue *tx_queue,
|
struct efx_tx_buffer *buffer)
|
{
|
unsigned int index = efx_tx_queue_get_insert_index(tx_queue);
|
struct efx_buffer *page_buf =
|
&tx_queue->cb_page[index >> (PAGE_SHIFT - EFX_TX_CB_ORDER)];
|
unsigned int offset =
|
((index << EFX_TX_CB_ORDER) + NET_IP_ALIGN) & (PAGE_SIZE - 1);
|
|
if (unlikely(!page_buf->addr) &&
|
efx_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE,
|
GFP_ATOMIC))
|
return NULL;
|
buffer->dma_addr = page_buf->dma_addr + offset;
|
buffer->unmap_len = 0;
|
return (u8 *)page_buf->addr + offset;
|
}
|
|
u8 *efx_tx_get_copy_buffer_limited(struct efx_tx_queue *tx_queue,
|
struct efx_tx_buffer *buffer, size_t len)
|
{
|
if (len > EFX_TX_CB_SIZE)
|
return NULL;
|
return efx_tx_get_copy_buffer(tx_queue, buffer);
|
}
|
|
static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1)
|
{
|
/* We need to consider all queues that the net core sees as one */
|
struct efx_nic *efx = txq1->efx;
|
struct efx_tx_queue *txq2;
|
unsigned int fill_level;
|
|
fill_level = efx_channel_tx_old_fill_level(txq1->channel);
|
if (likely(fill_level < efx->txq_stop_thresh))
|
return;
|
|
/* We used the stale old_read_count above, which gives us a
|
* pessimistic estimate of the fill level (which may even
|
* validly be >= efx->txq_entries). Now try again using
|
* read_count (more likely to be a cache miss).
|
*
|
* If we read read_count and then conditionally stop the
|
* queue, it is possible for the completion path to race with
|
* us and complete all outstanding descriptors in the middle,
|
* after which there will be no more completions to wake it.
|
* Therefore we stop the queue first, then read read_count
|
* (with a memory barrier to ensure the ordering), then
|
* restart the queue if the fill level turns out to be low
|
* enough.
|
*/
|
netif_tx_stop_queue(txq1->core_txq);
|
smp_mb();
|
efx_for_each_channel_tx_queue(txq2, txq1->channel)
|
txq2->old_read_count = READ_ONCE(txq2->read_count);
|
|
fill_level = efx_channel_tx_old_fill_level(txq1->channel);
|
EFX_WARN_ON_ONCE_PARANOID(fill_level >= efx->txq_entries);
|
if (likely(fill_level < efx->txq_stop_thresh)) {
|
smp_mb();
|
if (likely(!efx->loopback_selftest))
|
netif_tx_start_queue(txq1->core_txq);
|
}
|
}
|
|
static int efx_enqueue_skb_copy(struct efx_tx_queue *tx_queue,
|
struct sk_buff *skb)
|
{
|
unsigned int copy_len = skb->len;
|
struct efx_tx_buffer *buffer;
|
u8 *copy_buffer;
|
int rc;
|
|
EFX_WARN_ON_ONCE_PARANOID(copy_len > EFX_TX_CB_SIZE);
|
|
buffer = efx_tx_queue_get_insert_buffer(tx_queue);
|
|
copy_buffer = efx_tx_get_copy_buffer(tx_queue, buffer);
|
if (unlikely(!copy_buffer))
|
return -ENOMEM;
|
|
rc = skb_copy_bits(skb, 0, copy_buffer, copy_len);
|
EFX_WARN_ON_PARANOID(rc);
|
buffer->len = copy_len;
|
|
buffer->skb = skb;
|
buffer->flags = EFX_TX_BUF_SKB;
|
|
++tx_queue->insert_count;
|
return rc;
|
}
|
|
#ifdef EFX_USE_PIO
|
|
struct efx_short_copy_buffer {
|
int used;
|
u8 buf[L1_CACHE_BYTES];
|
};
|
|
/* Copy to PIO, respecting that writes to PIO buffers must be dword aligned.
|
* Advances piobuf pointer. Leaves additional data in the copy buffer.
|
*/
|
static void efx_memcpy_toio_aligned(struct efx_nic *efx, u8 __iomem **piobuf,
|
u8 *data, int len,
|
struct efx_short_copy_buffer *copy_buf)
|
{
|
int block_len = len & ~(sizeof(copy_buf->buf) - 1);
|
|
__iowrite64_copy(*piobuf, data, block_len >> 3);
|
*piobuf += block_len;
|
len -= block_len;
|
|
if (len) {
|
data += block_len;
|
BUG_ON(copy_buf->used);
|
BUG_ON(len > sizeof(copy_buf->buf));
|
memcpy(copy_buf->buf, data, len);
|
copy_buf->used = len;
|
}
|
}
|
|
/* Copy to PIO, respecting dword alignment, popping data from copy buffer first.
|
* Advances piobuf pointer. Leaves additional data in the copy buffer.
|
*/
|
static void efx_memcpy_toio_aligned_cb(struct efx_nic *efx, u8 __iomem **piobuf,
|
u8 *data, int len,
|
struct efx_short_copy_buffer *copy_buf)
|
{
|
if (copy_buf->used) {
|
/* if the copy buffer is partially full, fill it up and write */
|
int copy_to_buf =
|
min_t(int, sizeof(copy_buf->buf) - copy_buf->used, len);
|
|
memcpy(copy_buf->buf + copy_buf->used, data, copy_to_buf);
|
copy_buf->used += copy_to_buf;
|
|
/* if we didn't fill it up then we're done for now */
|
if (copy_buf->used < sizeof(copy_buf->buf))
|
return;
|
|
__iowrite64_copy(*piobuf, copy_buf->buf,
|
sizeof(copy_buf->buf) >> 3);
|
*piobuf += sizeof(copy_buf->buf);
|
data += copy_to_buf;
|
len -= copy_to_buf;
|
copy_buf->used = 0;
|
}
|
|
efx_memcpy_toio_aligned(efx, piobuf, data, len, copy_buf);
|
}
|
|
static void efx_flush_copy_buffer(struct efx_nic *efx, u8 __iomem *piobuf,
|
struct efx_short_copy_buffer *copy_buf)
|
{
|
/* if there's anything in it, write the whole buffer, including junk */
|
if (copy_buf->used)
|
__iowrite64_copy(piobuf, copy_buf->buf,
|
sizeof(copy_buf->buf) >> 3);
|
}
|
|
/* Traverse skb structure and copy fragments in to PIO buffer.
|
* Advances piobuf pointer.
|
*/
|
static void efx_skb_copy_bits_to_pio(struct efx_nic *efx, struct sk_buff *skb,
|
u8 __iomem **piobuf,
|
struct efx_short_copy_buffer *copy_buf)
|
{
|
int i;
|
|
efx_memcpy_toio_aligned(efx, piobuf, skb->data, skb_headlen(skb),
|
copy_buf);
|
|
for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
|
skb_frag_t *f = &skb_shinfo(skb)->frags[i];
|
u8 *vaddr;
|
|
vaddr = kmap_atomic(skb_frag_page(f));
|
|
efx_memcpy_toio_aligned_cb(efx, piobuf, vaddr + skb_frag_off(f),
|
skb_frag_size(f), copy_buf);
|
kunmap_atomic(vaddr);
|
}
|
|
EFX_WARN_ON_ONCE_PARANOID(skb_shinfo(skb)->frag_list);
|
}
|
|
static int efx_enqueue_skb_pio(struct efx_tx_queue *tx_queue,
|
struct sk_buff *skb)
|
{
|
struct efx_tx_buffer *buffer =
|
efx_tx_queue_get_insert_buffer(tx_queue);
|
u8 __iomem *piobuf = tx_queue->piobuf;
|
|
/* Copy to PIO buffer. Ensure the writes are padded to the end
|
* of a cache line, as this is required for write-combining to be
|
* effective on at least x86.
|
*/
|
|
if (skb_shinfo(skb)->nr_frags) {
|
/* The size of the copy buffer will ensure all writes
|
* are the size of a cache line.
|
*/
|
struct efx_short_copy_buffer copy_buf;
|
|
copy_buf.used = 0;
|
|
efx_skb_copy_bits_to_pio(tx_queue->efx, skb,
|
&piobuf, ©_buf);
|
efx_flush_copy_buffer(tx_queue->efx, piobuf, ©_buf);
|
} else {
|
/* Pad the write to the size of a cache line.
|
* We can do this because we know the skb_shared_info struct is
|
* after the source, and the destination buffer is big enough.
|
*/
|
BUILD_BUG_ON(L1_CACHE_BYTES >
|
SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
|
__iowrite64_copy(tx_queue->piobuf, skb->data,
|
ALIGN(skb->len, L1_CACHE_BYTES) >> 3);
|
}
|
|
buffer->skb = skb;
|
buffer->flags = EFX_TX_BUF_SKB | EFX_TX_BUF_OPTION;
|
|
EFX_POPULATE_QWORD_5(buffer->option,
|
ESF_DZ_TX_DESC_IS_OPT, 1,
|
ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_PIO,
|
ESF_DZ_TX_PIO_CONT, 0,
|
ESF_DZ_TX_PIO_BYTE_CNT, skb->len,
|
ESF_DZ_TX_PIO_BUF_ADDR,
|
tx_queue->piobuf_offset);
|
++tx_queue->insert_count;
|
return 0;
|
}
|
|
/* Decide whether we can use TX PIO, ie. write packet data directly into
|
* a buffer on the device. This can reduce latency at the expense of
|
* throughput, so we only do this if both hardware and software TX rings
|
* are empty, including all queues for the channel. This also ensures that
|
* only one packet at a time can be using the PIO buffer. If the xmit_more
|
* flag is set then we don't use this - there'll be another packet along
|
* shortly and we want to hold off the doorbell.
|
*/
|
static bool efx_tx_may_pio(struct efx_tx_queue *tx_queue)
|
{
|
struct efx_channel *channel = tx_queue->channel;
|
|
if (!tx_queue->piobuf)
|
return false;
|
|
EFX_WARN_ON_ONCE_PARANOID(!channel->efx->type->option_descriptors);
|
|
efx_for_each_channel_tx_queue(tx_queue, channel)
|
if (!efx_nic_tx_is_empty(tx_queue, tx_queue->packet_write_count))
|
return false;
|
|
return true;
|
}
|
#endif /* EFX_USE_PIO */
|
|
/* Send any pending traffic for a channel. xmit_more is shared across all
|
* queues for a channel, so we must check all of them.
|
*/
|
static void efx_tx_send_pending(struct efx_channel *channel)
|
{
|
struct efx_tx_queue *q;
|
|
efx_for_each_channel_tx_queue(q, channel) {
|
if (q->xmit_pending)
|
efx_nic_push_buffers(q);
|
}
|
}
|
|
/*
|
* Add a socket buffer to a TX queue
|
*
|
* This maps all fragments of a socket buffer for DMA and adds them to
|
* the TX queue. The queue's insert pointer will be incremented by
|
* the number of fragments in the socket buffer.
|
*
|
* If any DMA mapping fails, any mapped fragments will be unmapped,
|
* the queue's insert pointer will be restored to its original value.
|
*
|
* This function is split out from efx_hard_start_xmit to allow the
|
* loopback test to direct packets via specific TX queues.
|
*
|
* Returns NETDEV_TX_OK.
|
* You must hold netif_tx_lock() to call this function.
|
*/
|
netdev_tx_t __efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
|
{
|
unsigned int old_insert_count = tx_queue->insert_count;
|
bool xmit_more = netdev_xmit_more();
|
bool data_mapped = false;
|
unsigned int segments;
|
unsigned int skb_len;
|
int rc;
|
|
skb_len = skb->len;
|
segments = skb_is_gso(skb) ? skb_shinfo(skb)->gso_segs : 0;
|
if (segments == 1)
|
segments = 0; /* Don't use TSO for a single segment. */
|
|
/* Handle TSO first - it's *possible* (although unlikely) that we might
|
* be passed a packet to segment that's smaller than the copybreak/PIO
|
* size limit.
|
*/
|
if (segments) {
|
switch (tx_queue->tso_version) {
|
case 1:
|
rc = efx_enqueue_skb_tso(tx_queue, skb, &data_mapped);
|
break;
|
case 2:
|
rc = efx_ef10_tx_tso_desc(tx_queue, skb, &data_mapped);
|
break;
|
case 0: /* No TSO on this queue, SW fallback needed */
|
default:
|
rc = -EINVAL;
|
break;
|
}
|
if (rc == -EINVAL) {
|
rc = efx_tx_tso_fallback(tx_queue, skb);
|
tx_queue->tso_fallbacks++;
|
if (rc == 0)
|
return 0;
|
}
|
if (rc)
|
goto err;
|
#ifdef EFX_USE_PIO
|
} else if (skb_len <= efx_piobuf_size && !xmit_more &&
|
efx_tx_may_pio(tx_queue)) {
|
/* Use PIO for short packets with an empty queue. */
|
if (efx_enqueue_skb_pio(tx_queue, skb))
|
goto err;
|
tx_queue->pio_packets++;
|
data_mapped = true;
|
#endif
|
} else if (skb->data_len && skb_len <= EFX_TX_CB_SIZE) {
|
/* Pad short packets or coalesce short fragmented packets. */
|
if (efx_enqueue_skb_copy(tx_queue, skb))
|
goto err;
|
tx_queue->cb_packets++;
|
data_mapped = true;
|
}
|
|
/* Map for DMA and create descriptors if we haven't done so already. */
|
if (!data_mapped && (efx_tx_map_data(tx_queue, skb, segments)))
|
goto err;
|
|
efx_tx_maybe_stop_queue(tx_queue);
|
|
tx_queue->xmit_pending = true;
|
|
/* Pass off to hardware */
|
if (__netdev_tx_sent_queue(tx_queue->core_txq, skb_len, xmit_more))
|
efx_tx_send_pending(tx_queue->channel);
|
|
if (segments) {
|
tx_queue->tso_bursts++;
|
tx_queue->tso_packets += segments;
|
tx_queue->tx_packets += segments;
|
} else {
|
tx_queue->tx_packets++;
|
}
|
|
return NETDEV_TX_OK;
|
|
|
err:
|
efx_enqueue_unwind(tx_queue, old_insert_count);
|
dev_kfree_skb_any(skb);
|
|
/* If we're not expecting another transmit and we had something to push
|
* on this queue or a partner queue then we need to push here to get the
|
* previous packets out.
|
*/
|
if (!xmit_more)
|
efx_tx_send_pending(tx_queue->channel);
|
|
return NETDEV_TX_OK;
|
}
|
|
static void efx_xdp_return_frames(int n, struct xdp_frame **xdpfs)
|
{
|
int i;
|
|
for (i = 0; i < n; i++)
|
xdp_return_frame_rx_napi(xdpfs[i]);
|
}
|
|
/* Transmit a packet from an XDP buffer
|
*
|
* Returns number of packets sent on success, error code otherwise.
|
* Runs in NAPI context, either in our poll (for XDP TX) or a different NIC
|
* (for XDP redirect).
|
*/
|
int efx_xdp_tx_buffers(struct efx_nic *efx, int n, struct xdp_frame **xdpfs,
|
bool flush)
|
{
|
struct efx_tx_buffer *tx_buffer;
|
struct efx_tx_queue *tx_queue;
|
struct xdp_frame *xdpf;
|
dma_addr_t dma_addr;
|
unsigned int len;
|
int space;
|
int cpu;
|
int i;
|
|
cpu = raw_smp_processor_id();
|
|
if (!efx->xdp_tx_queue_count ||
|
unlikely(cpu >= efx->xdp_tx_queue_count))
|
return -EINVAL;
|
|
tx_queue = efx->xdp_tx_queues[cpu];
|
if (unlikely(!tx_queue))
|
return -EINVAL;
|
|
if (unlikely(n && !xdpfs))
|
return -EINVAL;
|
|
if (!n)
|
return 0;
|
|
/* Check for available space. We should never need multiple
|
* descriptors per frame.
|
*/
|
space = efx->txq_entries +
|
tx_queue->read_count - tx_queue->insert_count;
|
|
for (i = 0; i < n; i++) {
|
xdpf = xdpfs[i];
|
|
if (i >= space)
|
break;
|
|
/* We'll want a descriptor for this tx. */
|
prefetchw(__efx_tx_queue_get_insert_buffer(tx_queue));
|
|
len = xdpf->len;
|
|
/* Map for DMA. */
|
dma_addr = dma_map_single(&efx->pci_dev->dev,
|
xdpf->data, len,
|
DMA_TO_DEVICE);
|
if (dma_mapping_error(&efx->pci_dev->dev, dma_addr))
|
break;
|
|
/* Create descriptor and set up for unmapping DMA. */
|
tx_buffer = efx_tx_map_chunk(tx_queue, dma_addr, len);
|
tx_buffer->xdpf = xdpf;
|
tx_buffer->flags = EFX_TX_BUF_XDP |
|
EFX_TX_BUF_MAP_SINGLE;
|
tx_buffer->dma_offset = 0;
|
tx_buffer->unmap_len = len;
|
tx_queue->tx_packets++;
|
}
|
|
/* Pass mapped frames to hardware. */
|
if (flush && i > 0)
|
efx_nic_push_buffers(tx_queue);
|
|
if (i == 0)
|
return -EIO;
|
|
efx_xdp_return_frames(n - i, xdpfs + i);
|
|
return i;
|
}
|
|
/* Initiate a packet transmission. We use one channel per CPU
|
* (sharing when we have more CPUs than channels).
|
*
|
* Context: non-blocking.
|
* Should always return NETDEV_TX_OK and consume the skb.
|
*/
|
netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
|
struct net_device *net_dev)
|
{
|
struct efx_nic *efx = netdev_priv(net_dev);
|
struct efx_tx_queue *tx_queue;
|
unsigned index, type;
|
|
EFX_WARN_ON_PARANOID(!netif_device_present(net_dev));
|
|
index = skb_get_queue_mapping(skb);
|
type = efx_tx_csum_type_skb(skb);
|
if (index >= efx->n_tx_channels) {
|
index -= efx->n_tx_channels;
|
type |= EFX_TXQ_TYPE_HIGHPRI;
|
}
|
|
/* PTP "event" packet */
|
if (unlikely(efx_xmit_with_hwtstamp(skb)) &&
|
unlikely(efx_ptp_is_ptp_tx(efx, skb))) {
|
/* There may be existing transmits on the channel that are
|
* waiting for this packet to trigger the doorbell write.
|
* We need to send the packets at this point.
|
*/
|
efx_tx_send_pending(efx_get_tx_channel(efx, index));
|
return efx_ptp_tx(efx, skb);
|
}
|
|
tx_queue = efx_get_tx_queue(efx, index, type);
|
if (WARN_ON_ONCE(!tx_queue)) {
|
/* We don't have a TXQ of the right type.
|
* This should never happen, as we don't advertise offload
|
* features unless we can support them.
|
*/
|
dev_kfree_skb_any(skb);
|
/* If we're not expecting another transmit and we had something to push
|
* on this queue or a partner queue then we need to push here to get the
|
* previous packets out.
|
*/
|
if (!netdev_xmit_more())
|
efx_tx_send_pending(efx_get_tx_channel(efx, index));
|
return NETDEV_TX_OK;
|
}
|
|
return __efx_enqueue_skb(tx_queue, skb);
|
}
|
|
void efx_xmit_done_single(struct efx_tx_queue *tx_queue)
|
{
|
unsigned int pkts_compl = 0, bytes_compl = 0;
|
unsigned int read_ptr;
|
bool finished = false;
|
|
read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
|
|
while (!finished) {
|
struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
|
|
if (!efx_tx_buffer_in_use(buffer)) {
|
struct efx_nic *efx = tx_queue->efx;
|
|
netif_err(efx, hw, efx->net_dev,
|
"TX queue %d spurious single TX completion\n",
|
tx_queue->queue);
|
efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
|
return;
|
}
|
|
/* Need to check the flag before dequeueing. */
|
if (buffer->flags & EFX_TX_BUF_SKB)
|
finished = true;
|
efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
|
|
++tx_queue->read_count;
|
read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
|
}
|
|
tx_queue->pkts_compl += pkts_compl;
|
tx_queue->bytes_compl += bytes_compl;
|
|
EFX_WARN_ON_PARANOID(pkts_compl != 1);
|
|
efx_xmit_done_check_empty(tx_queue);
|
}
|
|
void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue)
|
{
|
struct efx_nic *efx = tx_queue->efx;
|
|
/* Must be inverse of queue lookup in efx_hard_start_xmit() */
|
tx_queue->core_txq =
|
netdev_get_tx_queue(efx->net_dev,
|
tx_queue->channel->channel +
|
((tx_queue->type & EFX_TXQ_TYPE_HIGHPRI) ?
|
efx->n_tx_channels : 0));
|
}
|
|
int efx_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
|
void *type_data)
|
{
|
struct efx_nic *efx = netdev_priv(net_dev);
|
struct tc_mqprio_qopt *mqprio = type_data;
|
unsigned tc, num_tc;
|
|
if (type != TC_SETUP_QDISC_MQPRIO)
|
return -EOPNOTSUPP;
|
|
/* Only Siena supported highpri queues */
|
if (efx_nic_rev(efx) > EFX_REV_SIENA_A0)
|
return -EOPNOTSUPP;
|
|
num_tc = mqprio->num_tc;
|
|
if (num_tc > EFX_MAX_TX_TC)
|
return -EINVAL;
|
|
mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
|
|
if (num_tc == net_dev->num_tc)
|
return 0;
|
|
for (tc = 0; tc < num_tc; tc++) {
|
net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels;
|
net_dev->tc_to_txq[tc].count = efx->n_tx_channels;
|
}
|
|
net_dev->num_tc = num_tc;
|
|
return netif_set_real_num_tx_queues(net_dev,
|
max_t(int, num_tc, 1) *
|
efx->n_tx_channels);
|
}
|
