/* SPDX-License-Identifier: GPL-2.0-only */
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/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2005-2006 Fen Systems Ltd.
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* Copyright 2006-2013 Solarflare Communications Inc.
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* Copyright 2019-2020 Xilinx Inc.
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*/
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#ifndef EFX_NIC_COMMON_H
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#define EFX_NIC_COMMON_H
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#include "net_driver.h"
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#include "efx_common.h"
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#include "mcdi.h"
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#include "ptp.h"
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enum {
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/* Revisions 0-2 were Falcon A0, A1 and B0 respectively.
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* They are not supported by this driver but these revision numbers
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* form part of the ethtool API for register dumping.
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*/
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EFX_REV_SIENA_A0 = 3,
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EFX_REV_HUNT_A0 = 4,
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EFX_REV_EF100 = 5,
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};
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static inline int efx_nic_rev(struct efx_nic *efx)
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{
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return efx->type->revision;
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}
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/* Read the current event from the event queue */
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static inline efx_qword_t *efx_event(struct efx_channel *channel,
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unsigned int index)
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{
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return ((efx_qword_t *) (channel->eventq.buf.addr)) +
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(index & channel->eventq_mask);
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}
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/* See if an event is present
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*
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* We check both the high and low dword of the event for all ones. We
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* wrote all ones when we cleared the event, and no valid event can
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* have all ones in either its high or low dwords. This approach is
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* robust against reordering.
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*
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* Note that using a single 64-bit comparison is incorrect; even
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* though the CPU read will be atomic, the DMA write may not be.
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*/
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static inline int efx_event_present(efx_qword_t *event)
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{
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return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
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EFX_DWORD_IS_ALL_ONES(event->dword[1]));
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}
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/* Returns a pointer to the specified transmit descriptor in the TX
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* descriptor queue belonging to the specified channel.
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*/
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static inline efx_qword_t *
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efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
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{
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return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
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}
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/* Report whether this TX queue would be empty for the given write_count.
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* May return false negative.
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*/
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static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, unsigned int write_count)
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{
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unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count);
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if (empty_read_count == 0)
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return false;
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return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
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}
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int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
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bool *data_mapped);
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/* Decide whether to push a TX descriptor to the NIC vs merely writing
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* the doorbell. This can reduce latency when we are adding a single
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* descriptor to an empty queue, but is otherwise pointless. Further,
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* Falcon and Siena have hardware bugs (SF bug 33851) that may be
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* triggered if we don't check this.
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* We use the write_count used for the last doorbell push, to get the
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* NIC's view of the tx queue.
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*/
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static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
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unsigned int write_count)
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{
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bool was_empty = efx_nic_tx_is_empty(tx_queue, write_count);
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tx_queue->empty_read_count = 0;
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return was_empty && tx_queue->write_count - write_count == 1;
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}
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/* Returns a pointer to the specified descriptor in the RX descriptor queue */
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static inline efx_qword_t *
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efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
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{
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return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
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}
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/* Alignment of PCIe DMA boundaries (4KB) */
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#define EFX_PAGE_SIZE 4096
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/* Size and alignment of buffer table entries (same) */
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#define EFX_BUF_SIZE EFX_PAGE_SIZE
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/* NIC-generic software stats */
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enum {
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GENERIC_STAT_rx_noskb_drops,
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GENERIC_STAT_rx_nodesc_trunc,
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GENERIC_STAT_COUNT
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};
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#define EFX_GENERIC_SW_STAT(ext_name) \
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[GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
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/* TX data path */
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static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
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{
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return tx_queue->efx->type->tx_probe(tx_queue);
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}
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static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
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{
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tx_queue->efx->type->tx_init(tx_queue);
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}
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static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
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{
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if (tx_queue->efx->type->tx_remove)
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tx_queue->efx->type->tx_remove(tx_queue);
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}
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static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
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{
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tx_queue->efx->type->tx_write(tx_queue);
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}
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/* RX data path */
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static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
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{
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return rx_queue->efx->type->rx_probe(rx_queue);
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}
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static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
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{
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rx_queue->efx->type->rx_init(rx_queue);
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}
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static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
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{
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rx_queue->efx->type->rx_remove(rx_queue);
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}
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static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
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{
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rx_queue->efx->type->rx_write(rx_queue);
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}
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static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
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{
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rx_queue->efx->type->rx_defer_refill(rx_queue);
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}
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/* Event data path */
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static inline int efx_nic_probe_eventq(struct efx_channel *channel)
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{
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return channel->efx->type->ev_probe(channel);
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}
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static inline int efx_nic_init_eventq(struct efx_channel *channel)
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{
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return channel->efx->type->ev_init(channel);
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}
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static inline void efx_nic_fini_eventq(struct efx_channel *channel)
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{
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channel->efx->type->ev_fini(channel);
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}
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static inline void efx_nic_remove_eventq(struct efx_channel *channel)
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{
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channel->efx->type->ev_remove(channel);
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}
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static inline int
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efx_nic_process_eventq(struct efx_channel *channel, int quota)
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{
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return channel->efx->type->ev_process(channel, quota);
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}
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static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
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{
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channel->efx->type->ev_read_ack(channel);
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}
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void efx_nic_event_test_start(struct efx_channel *channel);
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bool efx_nic_event_present(struct efx_channel *channel);
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static inline void efx_sensor_event(struct efx_nic *efx, efx_qword_t *ev)
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{
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if (efx->type->sensor_event)
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efx->type->sensor_event(efx, ev);
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}
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/* Some statistics are computed as A - B where A and B each increase
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* linearly with some hardware counter(s) and the counters are read
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* asynchronously. If the counters contributing to B are always read
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* after those contributing to A, the computed value may be lower than
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* the true value by some variable amount, and may decrease between
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* subsequent computations.
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*
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* We should never allow statistics to decrease or to exceed the true
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* value. Since the computed value will never be greater than the
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* true value, we can achieve this by only storing the computed value
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* when it increases.
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*/
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static inline void efx_update_diff_stat(u64 *stat, u64 diff)
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{
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if ((s64)(diff - *stat) > 0)
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*stat = diff;
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}
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/* Interrupts */
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int efx_nic_init_interrupt(struct efx_nic *efx);
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int efx_nic_irq_test_start(struct efx_nic *efx);
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void efx_nic_fini_interrupt(struct efx_nic *efx);
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static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
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{
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return READ_ONCE(channel->event_test_cpu);
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}
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static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
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{
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return READ_ONCE(efx->last_irq_cpu);
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}
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/* Global Resources */
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int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
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unsigned int len, gfp_t gfp_flags);
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void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
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size_t efx_nic_get_regs_len(struct efx_nic *efx);
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void efx_nic_get_regs(struct efx_nic *efx, void *buf);
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#define EFX_MC_STATS_GENERATION_INVALID ((__force __le64)(-1))
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size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
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const unsigned long *mask, u8 *names);
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int efx_nic_copy_stats(struct efx_nic *efx, __le64 *dest);
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void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
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const unsigned long *mask, u64 *stats,
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const void *dma_buf, bool accumulate);
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void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat);
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static inline size_t efx_nic_update_stats_atomic(struct efx_nic *efx, u64 *full_stats,
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struct rtnl_link_stats64 *core_stats)
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{
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if (efx->type->update_stats_atomic)
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return efx->type->update_stats_atomic(efx, full_stats, core_stats);
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return efx->type->update_stats(efx, full_stats, core_stats);
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}
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#define EFX_MAX_FLUSH_TIME 5000
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#endif /* EFX_NIC_COMMON_H */
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