// SPDX-License-Identifier: GPL-2.0-only
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/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2019 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include "net_driver.h"
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#include "efx.h"
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#include "nic.h"
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#include "mcdi_functions.h"
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#include "mcdi.h"
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#include "mcdi_pcol.h"
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int efx_mcdi_free_vis(struct efx_nic *efx)
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{
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MCDI_DECLARE_BUF_ERR(outbuf);
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size_t outlen;
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int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
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outbuf, sizeof(outbuf), &outlen);
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/* -EALREADY means nothing to free, so ignore */
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if (rc == -EALREADY)
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rc = 0;
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if (rc)
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efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
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rc);
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return rc;
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}
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int efx_mcdi_alloc_vis(struct efx_nic *efx, unsigned int min_vis,
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unsigned int max_vis, unsigned int *vi_base,
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unsigned int *allocated_vis)
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{
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MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
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MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
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size_t outlen;
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int rc;
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MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
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MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
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rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
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outbuf, sizeof(outbuf), &outlen);
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if (rc != 0)
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return rc;
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if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
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return -EIO;
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netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
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MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
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if (vi_base)
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*vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
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if (allocated_vis)
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*allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
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return 0;
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}
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int efx_mcdi_ev_probe(struct efx_channel *channel)
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{
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return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
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(channel->eventq_mask + 1) *
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sizeof(efx_qword_t),
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GFP_KERNEL);
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}
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int efx_mcdi_ev_init(struct efx_channel *channel, bool v1_cut_thru, bool v2)
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{
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MCDI_DECLARE_BUF(inbuf,
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MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
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EFX_BUF_SIZE));
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MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
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size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
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struct efx_nic *efx = channel->efx;
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size_t inlen, outlen;
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dma_addr_t dma_addr;
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int rc, i;
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/* Fill event queue with all ones (i.e. empty events) */
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memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
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MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
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MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
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/* INIT_EVQ expects index in vector table, not absolute */
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MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
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MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
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MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
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MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
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MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
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MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
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MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
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MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
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if (v2) {
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/* Use the new generic approach to specifying event queue
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* configuration, requesting lower latency or higher throughput.
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* The options that actually get used appear in the output.
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*/
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MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
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INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
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INIT_EVQ_V2_IN_FLAG_TYPE,
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MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
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} else {
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MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
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INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
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INIT_EVQ_IN_FLAG_RX_MERGE, 1,
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INIT_EVQ_IN_FLAG_TX_MERGE, 1,
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INIT_EVQ_IN_FLAG_CUT_THRU, v1_cut_thru);
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}
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dma_addr = channel->eventq.buf.dma_addr;
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for (i = 0; i < entries; ++i) {
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MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
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dma_addr += EFX_BUF_SIZE;
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}
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inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
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rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
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outbuf, sizeof(outbuf), &outlen);
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if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
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netif_dbg(efx, drv, efx->net_dev,
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"Channel %d using event queue flags %08x\n",
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channel->channel,
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MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
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return rc;
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}
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void efx_mcdi_ev_remove(struct efx_channel *channel)
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{
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efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
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}
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void efx_mcdi_ev_fini(struct efx_channel *channel)
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{
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MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
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MCDI_DECLARE_BUF_ERR(outbuf);
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struct efx_nic *efx = channel->efx;
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size_t outlen;
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int rc;
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MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
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rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
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outbuf, sizeof(outbuf), &outlen);
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if (rc && rc != -EALREADY)
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goto fail;
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return;
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fail:
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efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
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outbuf, outlen, rc);
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}
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int efx_mcdi_tx_init(struct efx_tx_queue *tx_queue)
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{
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MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
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EFX_BUF_SIZE));
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bool csum_offload = tx_queue->type & EFX_TXQ_TYPE_OUTER_CSUM;
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bool inner_csum = tx_queue->type & EFX_TXQ_TYPE_INNER_CSUM;
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size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
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struct efx_channel *channel = tx_queue->channel;
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struct efx_nic *efx = tx_queue->efx;
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dma_addr_t dma_addr;
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size_t inlen;
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int rc, i;
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BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
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MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
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MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
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MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->label);
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MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
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MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
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MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, efx->vport_id);
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dma_addr = tx_queue->txd.buf.dma_addr;
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netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
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tx_queue->queue, entries, (u64)dma_addr);
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for (i = 0; i < entries; ++i) {
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MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
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dma_addr += EFX_BUF_SIZE;
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}
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inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
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do {
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bool tso_v2 = tx_queue->tso_version == 2;
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/* TSOv2 implies IP header checksum offload for TSO frames,
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* so we can safely disable IP header checksum offload for
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* everything else. If we don't have TSOv2, then we have to
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* enable IP header checksum offload, which is strictly
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* incorrect but better than breaking TSO.
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*/
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MCDI_POPULATE_DWORD_6(inbuf, INIT_TXQ_IN_FLAGS,
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/* This flag was removed from mcdi_pcol.h for
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* the non-_EXT version of INIT_TXQ. However,
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* firmware still honours it.
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*/
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INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
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INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !(csum_offload && tso_v2),
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INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload,
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INIT_TXQ_EXT_IN_FLAG_TIMESTAMP, tx_queue->timestamping,
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INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN, inner_csum && !tso_v2,
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INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN, inner_csum);
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rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
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NULL, 0, NULL);
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if (rc == -ENOSPC && tso_v2) {
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/* Retry without TSOv2 if we're short on contexts. */
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tx_queue->tso_version = 0;
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netif_warn(efx, probe, efx->net_dev,
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"TSOv2 context not available to segment in "
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"hardware. TCP performance may be reduced.\n"
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);
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} else if (rc) {
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efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
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MC_CMD_INIT_TXQ_EXT_IN_LEN,
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NULL, 0, rc);
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goto fail;
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}
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} while (rc);
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return 0;
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fail:
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return rc;
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}
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void efx_mcdi_tx_remove(struct efx_tx_queue *tx_queue)
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{
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efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
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}
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void efx_mcdi_tx_fini(struct efx_tx_queue *tx_queue)
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{
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MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
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MCDI_DECLARE_BUF_ERR(outbuf);
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struct efx_nic *efx = tx_queue->efx;
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size_t outlen;
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int rc;
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MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
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tx_queue->queue);
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rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
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outbuf, sizeof(outbuf), &outlen);
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if (rc && rc != -EALREADY)
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goto fail;
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return;
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fail:
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efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
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outbuf, outlen, rc);
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}
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int efx_mcdi_rx_probe(struct efx_rx_queue *rx_queue)
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{
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return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
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(rx_queue->ptr_mask + 1) *
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sizeof(efx_qword_t),
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GFP_KERNEL);
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}
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void efx_mcdi_rx_init(struct efx_rx_queue *rx_queue)
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{
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struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
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size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
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MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_RXQ_V4_IN_LEN);
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struct efx_nic *efx = rx_queue->efx;
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unsigned int buffer_size;
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dma_addr_t dma_addr;
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int rc;
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int i;
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BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
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rx_queue->scatter_n = 0;
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rx_queue->scatter_len = 0;
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if (efx->type->revision == EFX_REV_EF100)
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buffer_size = efx->rx_page_buf_step;
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else
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buffer_size = 0;
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MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
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MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
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MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
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MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
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efx_rx_queue_index(rx_queue));
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MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
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INIT_RXQ_IN_FLAG_PREFIX, 1,
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INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
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MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
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MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, efx->vport_id);
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MCDI_SET_DWORD(inbuf, INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES, buffer_size);
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dma_addr = rx_queue->rxd.buf.dma_addr;
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netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
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efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
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for (i = 0; i < entries; ++i) {
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MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
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dma_addr += EFX_BUF_SIZE;
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}
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rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, sizeof(inbuf),
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NULL, 0, NULL);
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if (rc)
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netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
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efx_rx_queue_index(rx_queue));
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}
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void efx_mcdi_rx_remove(struct efx_rx_queue *rx_queue)
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{
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efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
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}
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void efx_mcdi_rx_fini(struct efx_rx_queue *rx_queue)
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{
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MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
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MCDI_DECLARE_BUF_ERR(outbuf);
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struct efx_nic *efx = rx_queue->efx;
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size_t outlen;
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int rc;
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MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
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efx_rx_queue_index(rx_queue));
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rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
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outbuf, sizeof(outbuf), &outlen);
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if (rc && rc != -EALREADY)
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goto fail;
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return;
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fail:
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efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
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outbuf, outlen, rc);
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}
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int efx_fini_dmaq(struct efx_nic *efx)
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{
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struct efx_tx_queue *tx_queue;
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struct efx_rx_queue *rx_queue;
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struct efx_channel *channel;
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int pending;
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/* If the MC has just rebooted, the TX/RX queues will have already been
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* torn down, but efx->active_queues needs to be set to zero.
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*/
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if (efx->must_realloc_vis) {
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atomic_set(&efx->active_queues, 0);
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return 0;
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}
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/* Do not attempt to write to the NIC during EEH recovery */
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if (efx->state != STATE_RECOVERY) {
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efx_for_each_channel(channel, efx) {
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efx_for_each_channel_rx_queue(rx_queue, channel)
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efx_mcdi_rx_fini(rx_queue);
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efx_for_each_channel_tx_queue(tx_queue, channel)
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efx_mcdi_tx_fini(tx_queue);
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}
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wait_event_timeout(efx->flush_wq,
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atomic_read(&efx->active_queues) == 0,
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msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
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pending = atomic_read(&efx->active_queues);
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if (pending) {
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netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
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pending);
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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int efx_mcdi_window_mode_to_stride(struct efx_nic *efx, u8 vi_window_mode)
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{
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switch (vi_window_mode) {
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case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
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efx->vi_stride = 8192;
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break;
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case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
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efx->vi_stride = 16384;
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break;
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case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
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efx->vi_stride = 65536;
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break;
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default:
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netif_err(efx, probe, efx->net_dev,
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"Unrecognised VI window mode %d\n",
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vi_window_mode);
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return -EIO;
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}
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netif_dbg(efx, probe, efx->net_dev, "vi_stride = %u\n",
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efx->vi_stride);
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return 0;
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}
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int efx_get_pf_index(struct efx_nic *efx, unsigned int *pf_index)
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{
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MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
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size_t outlen;
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int rc;
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rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
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sizeof(outbuf), &outlen);
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if (rc)
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return rc;
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if (outlen < sizeof(outbuf))
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return -EIO;
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*pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
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return 0;
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}
|
