// SPDX-License-Identifier: GPL-2.0-only
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/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2018 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include "net_driver.h"
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#include <linux/module.h>
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#include "efx_channels.h"
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#include "efx.h"
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#include "efx_common.h"
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#include "tx_common.h"
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#include "rx_common.h"
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#include "nic.h"
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#include "sriov.h"
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/* This is the first interrupt mode to try out of:
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* 0 => MSI-X
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* 1 => MSI
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* 2 => legacy
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*/
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unsigned int efx_interrupt_mode = EFX_INT_MODE_MSIX;
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/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
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* i.e. the number of CPUs among which we may distribute simultaneous
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* interrupt handling.
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*
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* Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
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* The default (0) means to assign an interrupt to each core.
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*/
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unsigned int rss_cpus;
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static unsigned int irq_adapt_low_thresh = 8000;
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module_param(irq_adapt_low_thresh, uint, 0644);
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MODULE_PARM_DESC(irq_adapt_low_thresh,
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"Threshold score for reducing IRQ moderation");
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static unsigned int irq_adapt_high_thresh = 16000;
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module_param(irq_adapt_high_thresh, uint, 0644);
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MODULE_PARM_DESC(irq_adapt_high_thresh,
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"Threshold score for increasing IRQ moderation");
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/* This is the weight assigned to each of the (per-channel) virtual
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* NAPI devices.
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*/
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static int napi_weight = 64;
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/***************
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* Housekeeping
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***************/
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int efx_channel_dummy_op_int(struct efx_channel *channel)
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{
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return 0;
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}
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void efx_channel_dummy_op_void(struct efx_channel *channel)
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{
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}
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static const struct efx_channel_type efx_default_channel_type = {
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.pre_probe = efx_channel_dummy_op_int,
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.post_remove = efx_channel_dummy_op_void,
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.get_name = efx_get_channel_name,
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.copy = efx_copy_channel,
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.want_txqs = efx_default_channel_want_txqs,
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.keep_eventq = false,
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.want_pio = true,
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};
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/*************
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* INTERRUPTS
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*************/
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static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
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{
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cpumask_var_t thread_mask;
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unsigned int count;
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int cpu;
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if (rss_cpus) {
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count = rss_cpus;
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} else {
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if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
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netif_warn(efx, probe, efx->net_dev,
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"RSS disabled due to allocation failure\n");
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return 1;
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}
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count = 0;
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for_each_online_cpu(cpu) {
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if (!cpumask_test_cpu(cpu, thread_mask)) {
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++count;
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cpumask_or(thread_mask, thread_mask,
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topology_sibling_cpumask(cpu));
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}
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}
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free_cpumask_var(thread_mask);
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}
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if (count > EFX_MAX_RX_QUEUES) {
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netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn,
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"Reducing number of rx queues from %u to %u.\n",
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count, EFX_MAX_RX_QUEUES);
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count = EFX_MAX_RX_QUEUES;
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}
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/* If RSS is requested for the PF *and* VFs then we can't write RSS
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* table entries that are inaccessible to VFs
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*/
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#ifdef CONFIG_SFC_SRIOV
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if (efx->type->sriov_wanted) {
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if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
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count > efx_vf_size(efx)) {
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netif_warn(efx, probe, efx->net_dev,
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"Reducing number of RSS channels from %u to %u for "
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"VF support. Increase vf-msix-limit to use more "
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"channels on the PF.\n",
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count, efx_vf_size(efx));
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count = efx_vf_size(efx);
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}
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}
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#endif
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return count;
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}
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static int efx_allocate_msix_channels(struct efx_nic *efx,
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unsigned int max_channels,
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unsigned int extra_channels,
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unsigned int parallelism)
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{
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unsigned int n_channels = parallelism;
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int vec_count;
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int n_xdp_tx;
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int n_xdp_ev;
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if (efx_separate_tx_channels)
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n_channels *= 2;
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n_channels += extra_channels;
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/* To allow XDP transmit to happen from arbitrary NAPI contexts
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* we allocate a TX queue per CPU. We share event queues across
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* multiple tx queues, assuming tx and ev queues are both
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* maximum size.
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*/
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n_xdp_tx = num_possible_cpus();
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n_xdp_ev = DIV_ROUND_UP(n_xdp_tx, EFX_MAX_TXQ_PER_CHANNEL);
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vec_count = pci_msix_vec_count(efx->pci_dev);
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if (vec_count < 0)
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return vec_count;
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max_channels = min_t(unsigned int, vec_count, max_channels);
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/* Check resources.
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* We need a channel per event queue, plus a VI per tx queue.
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* This may be more pessimistic than it needs to be.
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*/
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if (n_channels + n_xdp_ev > max_channels) {
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netif_err(efx, drv, efx->net_dev,
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"Insufficient resources for %d XDP event queues (%d other channels, max %d)\n",
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n_xdp_ev, n_channels, max_channels);
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efx->n_xdp_channels = 0;
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efx->xdp_tx_per_channel = 0;
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efx->xdp_tx_queue_count = 0;
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} else if (n_channels + n_xdp_tx > efx->max_vis) {
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netif_err(efx, drv, efx->net_dev,
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"Insufficient resources for %d XDP TX queues (%d other channels, max VIs %d)\n",
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n_xdp_tx, n_channels, efx->max_vis);
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efx->n_xdp_channels = 0;
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efx->xdp_tx_per_channel = 0;
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efx->xdp_tx_queue_count = 0;
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} else {
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efx->n_xdp_channels = n_xdp_ev;
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efx->xdp_tx_per_channel = EFX_MAX_TXQ_PER_CHANNEL;
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efx->xdp_tx_queue_count = n_xdp_tx;
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n_channels += n_xdp_ev;
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netif_dbg(efx, drv, efx->net_dev,
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"Allocating %d TX and %d event queues for XDP\n",
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n_xdp_tx, n_xdp_ev);
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}
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if (vec_count < n_channels) {
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netif_err(efx, drv, efx->net_dev,
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"WARNING: Insufficient MSI-X vectors available (%d < %u).\n",
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vec_count, n_channels);
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netif_err(efx, drv, efx->net_dev,
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"WARNING: Performance may be reduced.\n");
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n_channels = vec_count;
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}
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n_channels = min(n_channels, max_channels);
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efx->n_channels = n_channels;
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/* Ignore XDP tx channels when creating rx channels. */
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n_channels -= efx->n_xdp_channels;
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if (efx_separate_tx_channels) {
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efx->n_tx_channels =
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min(max(n_channels / 2, 1U),
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efx->max_tx_channels);
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efx->tx_channel_offset =
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n_channels - efx->n_tx_channels;
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efx->n_rx_channels =
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max(n_channels -
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efx->n_tx_channels, 1U);
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} else {
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efx->n_tx_channels = min(n_channels, efx->max_tx_channels);
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efx->tx_channel_offset = 0;
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efx->n_rx_channels = n_channels;
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}
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efx->n_rx_channels = min(efx->n_rx_channels, parallelism);
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efx->n_tx_channels = min(efx->n_tx_channels, parallelism);
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efx->xdp_channel_offset = n_channels;
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netif_dbg(efx, drv, efx->net_dev,
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"Allocating %u RX channels\n",
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efx->n_rx_channels);
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return efx->n_channels;
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}
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/* Probe the number and type of interrupts we are able to obtain, and
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* the resulting numbers of channels and RX queues.
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*/
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int efx_probe_interrupts(struct efx_nic *efx)
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{
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unsigned int extra_channels = 0;
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unsigned int rss_spread;
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unsigned int i, j;
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int rc;
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for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
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if (efx->extra_channel_type[i])
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++extra_channels;
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if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
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unsigned int parallelism = efx_wanted_parallelism(efx);
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struct msix_entry xentries[EFX_MAX_CHANNELS];
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unsigned int n_channels;
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rc = efx_allocate_msix_channels(efx, efx->max_channels,
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extra_channels, parallelism);
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if (rc >= 0) {
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n_channels = rc;
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for (i = 0; i < n_channels; i++)
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xentries[i].entry = i;
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rc = pci_enable_msix_range(efx->pci_dev, xentries, 1,
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n_channels);
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}
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if (rc < 0) {
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/* Fall back to single channel MSI */
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netif_err(efx, drv, efx->net_dev,
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"could not enable MSI-X\n");
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if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI)
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efx->interrupt_mode = EFX_INT_MODE_MSI;
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else
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return rc;
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} else if (rc < n_channels) {
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netif_err(efx, drv, efx->net_dev,
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"WARNING: Insufficient MSI-X vectors"
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" available (%d < %u).\n", rc, n_channels);
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netif_err(efx, drv, efx->net_dev,
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"WARNING: Performance may be reduced.\n");
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n_channels = rc;
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}
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if (rc > 0) {
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for (i = 0; i < efx->n_channels; i++)
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efx_get_channel(efx, i)->irq =
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xentries[i].vector;
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}
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}
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/* Try single interrupt MSI */
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if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
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efx->n_channels = 1;
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efx->n_rx_channels = 1;
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efx->n_tx_channels = 1;
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efx->tx_channel_offset = 0;
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efx->n_xdp_channels = 0;
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efx->xdp_channel_offset = efx->n_channels;
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rc = pci_enable_msi(efx->pci_dev);
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if (rc == 0) {
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efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
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} else {
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netif_err(efx, drv, efx->net_dev,
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"could not enable MSI\n");
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if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY)
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efx->interrupt_mode = EFX_INT_MODE_LEGACY;
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else
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return rc;
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}
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}
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/* Assume legacy interrupts */
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if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
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efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0);
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efx->n_rx_channels = 1;
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efx->n_tx_channels = 1;
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efx->tx_channel_offset = efx_separate_tx_channels ? 1 : 0;
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efx->n_xdp_channels = 0;
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efx->xdp_channel_offset = efx->n_channels;
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efx->legacy_irq = efx->pci_dev->irq;
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}
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/* Assign extra channels if possible, before XDP channels */
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efx->n_extra_tx_channels = 0;
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j = efx->xdp_channel_offset;
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for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
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if (!efx->extra_channel_type[i])
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continue;
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if (j <= efx->tx_channel_offset + efx->n_tx_channels) {
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efx->extra_channel_type[i]->handle_no_channel(efx);
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} else {
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--j;
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efx_get_channel(efx, j)->type =
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efx->extra_channel_type[i];
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if (efx_channel_has_tx_queues(efx_get_channel(efx, j)))
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efx->n_extra_tx_channels++;
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}
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}
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rss_spread = efx->n_rx_channels;
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/* RSS might be usable on VFs even if it is disabled on the PF */
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#ifdef CONFIG_SFC_SRIOV
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if (efx->type->sriov_wanted) {
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efx->rss_spread = ((rss_spread > 1 ||
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!efx->type->sriov_wanted(efx)) ?
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rss_spread : efx_vf_size(efx));
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return 0;
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}
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#endif
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efx->rss_spread = rss_spread;
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return 0;
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}
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#if defined(CONFIG_SMP)
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void efx_set_interrupt_affinity(struct efx_nic *efx)
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{
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struct efx_channel *channel;
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unsigned int cpu;
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efx_for_each_channel(channel, efx) {
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cpu = cpumask_local_spread(channel->channel,
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pcibus_to_node(efx->pci_dev->bus));
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irq_set_affinity_hint(channel->irq, cpumask_of(cpu));
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}
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}
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void efx_clear_interrupt_affinity(struct efx_nic *efx)
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{
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struct efx_channel *channel;
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efx_for_each_channel(channel, efx)
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irq_set_affinity_hint(channel->irq, NULL);
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}
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#else
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void
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efx_set_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused)))
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{
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}
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void
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efx_clear_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused)))
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{
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}
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#endif /* CONFIG_SMP */
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void efx_remove_interrupts(struct efx_nic *efx)
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{
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struct efx_channel *channel;
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/* Remove MSI/MSI-X interrupts */
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efx_for_each_channel(channel, efx)
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channel->irq = 0;
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pci_disable_msi(efx->pci_dev);
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pci_disable_msix(efx->pci_dev);
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/* Remove legacy interrupt */
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efx->legacy_irq = 0;
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}
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/***************
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* EVENT QUEUES
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***************/
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/* Create event queue
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* Event queue memory allocations are done only once. If the channel
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* is reset, the memory buffer will be reused; this guards against
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* errors during channel reset and also simplifies interrupt handling.
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*/
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int efx_probe_eventq(struct efx_channel *channel)
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{
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struct efx_nic *efx = channel->efx;
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unsigned long entries;
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netif_dbg(efx, probe, efx->net_dev,
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"chan %d create event queue\n", channel->channel);
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/* Build an event queue with room for one event per tx and rx buffer,
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* plus some extra for link state events and MCDI completions.
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*/
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entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
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EFX_WARN_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
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channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
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return efx_nic_probe_eventq(channel);
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}
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/* Prepare channel's event queue */
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int efx_init_eventq(struct efx_channel *channel)
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{
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struct efx_nic *efx = channel->efx;
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int rc;
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EFX_WARN_ON_PARANOID(channel->eventq_init);
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netif_dbg(efx, drv, efx->net_dev,
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"chan %d init event queue\n", channel->channel);
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rc = efx_nic_init_eventq(channel);
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if (rc == 0) {
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efx->type->push_irq_moderation(channel);
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channel->eventq_read_ptr = 0;
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channel->eventq_init = true;
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}
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return rc;
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}
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/* Enable event queue processing and NAPI */
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void efx_start_eventq(struct efx_channel *channel)
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{
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netif_dbg(channel->efx, ifup, channel->efx->net_dev,
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"chan %d start event queue\n", channel->channel);
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/* Make sure the NAPI handler sees the enabled flag set */
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channel->enabled = true;
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smp_wmb();
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napi_enable(&channel->napi_str);
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efx_nic_eventq_read_ack(channel);
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}
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/* Disable event queue processing and NAPI */
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void efx_stop_eventq(struct efx_channel *channel)
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{
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if (!channel->enabled)
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return;
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napi_disable(&channel->napi_str);
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channel->enabled = false;
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}
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void efx_fini_eventq(struct efx_channel *channel)
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{
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if (!channel->eventq_init)
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return;
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netif_dbg(channel->efx, drv, channel->efx->net_dev,
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"chan %d fini event queue\n", channel->channel);
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efx_nic_fini_eventq(channel);
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channel->eventq_init = false;
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}
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void efx_remove_eventq(struct efx_channel *channel)
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{
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netif_dbg(channel->efx, drv, channel->efx->net_dev,
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"chan %d remove event queue\n", channel->channel);
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efx_nic_remove_eventq(channel);
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}
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/**************************************************************************
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*
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* Channel handling
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*
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*************************************************************************/
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#ifdef CONFIG_RFS_ACCEL
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static void efx_filter_rfs_expire(struct work_struct *data)
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{
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struct delayed_work *dwork = to_delayed_work(data);
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struct efx_channel *channel;
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unsigned int time, quota;
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channel = container_of(dwork, struct efx_channel, filter_work);
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time = jiffies - channel->rfs_last_expiry;
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quota = channel->rfs_filter_count * time / (30 * HZ);
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if (quota >= 20 && __efx_filter_rfs_expire(channel, min(channel->rfs_filter_count, quota)))
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channel->rfs_last_expiry += time;
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/* Ensure we do more work eventually even if NAPI poll is not happening */
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schedule_delayed_work(dwork, 30 * HZ);
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}
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#endif
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/* Allocate and initialise a channel structure. */
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static struct efx_channel *efx_alloc_channel(struct efx_nic *efx, int i)
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{
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struct efx_rx_queue *rx_queue;
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struct efx_tx_queue *tx_queue;
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struct efx_channel *channel;
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int j;
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channel = kzalloc(sizeof(*channel), GFP_KERNEL);
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if (!channel)
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return NULL;
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channel->efx = efx;
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channel->channel = i;
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channel->type = &efx_default_channel_type;
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for (j = 0; j < EFX_MAX_TXQ_PER_CHANNEL; j++) {
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tx_queue = &channel->tx_queue[j];
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tx_queue->efx = efx;
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tx_queue->queue = -1;
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tx_queue->label = j;
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tx_queue->channel = channel;
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}
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#ifdef CONFIG_RFS_ACCEL
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INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire);
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#endif
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rx_queue = &channel->rx_queue;
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rx_queue->efx = efx;
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timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0);
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return channel;
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}
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int efx_init_channels(struct efx_nic *efx)
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{
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unsigned int i;
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for (i = 0; i < EFX_MAX_CHANNELS; i++) {
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efx->channel[i] = efx_alloc_channel(efx, i);
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if (!efx->channel[i])
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return -ENOMEM;
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efx->msi_context[i].efx = efx;
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efx->msi_context[i].index = i;
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}
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/* Higher numbered interrupt modes are less capable! */
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efx->interrupt_mode = min(efx->type->min_interrupt_mode,
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efx_interrupt_mode);
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efx->max_channels = EFX_MAX_CHANNELS;
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efx->max_tx_channels = EFX_MAX_CHANNELS;
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return 0;
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}
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void efx_fini_channels(struct efx_nic *efx)
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{
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unsigned int i;
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for (i = 0; i < EFX_MAX_CHANNELS; i++)
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if (efx->channel[i]) {
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kfree(efx->channel[i]);
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efx->channel[i] = NULL;
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}
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}
|
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/* Allocate and initialise a channel structure, copying parameters
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* (but not resources) from an old channel structure.
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*/
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struct efx_channel *efx_copy_channel(const struct efx_channel *old_channel)
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{
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struct efx_rx_queue *rx_queue;
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struct efx_tx_queue *tx_queue;
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struct efx_channel *channel;
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int j;
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channel = kmalloc(sizeof(*channel), GFP_KERNEL);
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if (!channel)
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return NULL;
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*channel = *old_channel;
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channel->napi_dev = NULL;
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INIT_HLIST_NODE(&channel->napi_str.napi_hash_node);
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channel->napi_str.napi_id = 0;
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channel->napi_str.state = 0;
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memset(&channel->eventq, 0, sizeof(channel->eventq));
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for (j = 0; j < EFX_MAX_TXQ_PER_CHANNEL; j++) {
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tx_queue = &channel->tx_queue[j];
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if (tx_queue->channel)
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tx_queue->channel = channel;
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tx_queue->buffer = NULL;
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tx_queue->cb_page = NULL;
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memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
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}
|
|
rx_queue = &channel->rx_queue;
|
rx_queue->buffer = NULL;
|
memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
|
timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0);
|
#ifdef CONFIG_RFS_ACCEL
|
INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire);
|
#endif
|
|
return channel;
|
}
|
|
static int efx_probe_channel(struct efx_channel *channel)
|
{
|
struct efx_tx_queue *tx_queue;
|
struct efx_rx_queue *rx_queue;
|
int rc;
|
|
netif_dbg(channel->efx, probe, channel->efx->net_dev,
|
"creating channel %d\n", channel->channel);
|
|
rc = channel->type->pre_probe(channel);
|
if (rc)
|
goto fail;
|
|
rc = efx_probe_eventq(channel);
|
if (rc)
|
goto fail;
|
|
efx_for_each_channel_tx_queue(tx_queue, channel) {
|
rc = efx_probe_tx_queue(tx_queue);
|
if (rc)
|
goto fail;
|
}
|
|
efx_for_each_channel_rx_queue(rx_queue, channel) {
|
rc = efx_probe_rx_queue(rx_queue);
|
if (rc)
|
goto fail;
|
}
|
|
channel->rx_list = NULL;
|
|
return 0;
|
|
fail:
|
efx_remove_channel(channel);
|
return rc;
|
}
|
|
void efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
|
{
|
struct efx_nic *efx = channel->efx;
|
const char *type;
|
int number;
|
|
number = channel->channel;
|
|
if (number >= efx->xdp_channel_offset &&
|
!WARN_ON_ONCE(!efx->n_xdp_channels)) {
|
type = "-xdp";
|
number -= efx->xdp_channel_offset;
|
} else if (efx->tx_channel_offset == 0) {
|
type = "";
|
} else if (number < efx->tx_channel_offset) {
|
type = "-rx";
|
} else {
|
type = "-tx";
|
number -= efx->tx_channel_offset;
|
}
|
snprintf(buf, len, "%s%s-%d", efx->name, type, number);
|
}
|
|
void efx_set_channel_names(struct efx_nic *efx)
|
{
|
struct efx_channel *channel;
|
|
efx_for_each_channel(channel, efx)
|
channel->type->get_name(channel,
|
efx->msi_context[channel->channel].name,
|
sizeof(efx->msi_context[0].name));
|
}
|
|
int efx_probe_channels(struct efx_nic *efx)
|
{
|
struct efx_channel *channel;
|
int rc;
|
|
/* Restart special buffer allocation */
|
efx->next_buffer_table = 0;
|
|
/* Probe channels in reverse, so that any 'extra' channels
|
* use the start of the buffer table. This allows the traffic
|
* channels to be resized without moving them or wasting the
|
* entries before them.
|
*/
|
efx_for_each_channel_rev(channel, efx) {
|
rc = efx_probe_channel(channel);
|
if (rc) {
|
netif_err(efx, probe, efx->net_dev,
|
"failed to create channel %d\n",
|
channel->channel);
|
goto fail;
|
}
|
}
|
efx_set_channel_names(efx);
|
|
return 0;
|
|
fail:
|
efx_remove_channels(efx);
|
return rc;
|
}
|
|
void efx_remove_channel(struct efx_channel *channel)
|
{
|
struct efx_tx_queue *tx_queue;
|
struct efx_rx_queue *rx_queue;
|
|
netif_dbg(channel->efx, drv, channel->efx->net_dev,
|
"destroy chan %d\n", channel->channel);
|
|
efx_for_each_channel_rx_queue(rx_queue, channel)
|
efx_remove_rx_queue(rx_queue);
|
efx_for_each_channel_tx_queue(tx_queue, channel)
|
efx_remove_tx_queue(tx_queue);
|
efx_remove_eventq(channel);
|
channel->type->post_remove(channel);
|
}
|
|
void efx_remove_channels(struct efx_nic *efx)
|
{
|
struct efx_channel *channel;
|
|
efx_for_each_channel(channel, efx)
|
efx_remove_channel(channel);
|
|
kfree(efx->xdp_tx_queues);
|
}
|
|
int efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
|
{
|
struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel,
|
*ptp_channel = efx_ptp_channel(efx);
|
struct efx_ptp_data *ptp_data = efx->ptp_data;
|
unsigned int i, next_buffer_table = 0;
|
u32 old_rxq_entries, old_txq_entries;
|
int rc, rc2;
|
|
rc = efx_check_disabled(efx);
|
if (rc)
|
return rc;
|
|
/* Not all channels should be reallocated. We must avoid
|
* reallocating their buffer table entries.
|
*/
|
efx_for_each_channel(channel, efx) {
|
struct efx_rx_queue *rx_queue;
|
struct efx_tx_queue *tx_queue;
|
|
if (channel->type->copy)
|
continue;
|
next_buffer_table = max(next_buffer_table,
|
channel->eventq.index +
|
channel->eventq.entries);
|
efx_for_each_channel_rx_queue(rx_queue, channel)
|
next_buffer_table = max(next_buffer_table,
|
rx_queue->rxd.index +
|
rx_queue->rxd.entries);
|
efx_for_each_channel_tx_queue(tx_queue, channel)
|
next_buffer_table = max(next_buffer_table,
|
tx_queue->txd.index +
|
tx_queue->txd.entries);
|
}
|
|
efx_device_detach_sync(efx);
|
efx_stop_all(efx);
|
efx_soft_disable_interrupts(efx);
|
|
/* Clone channels (where possible) */
|
memset(other_channel, 0, sizeof(other_channel));
|
for (i = 0; i < efx->n_channels; i++) {
|
channel = efx->channel[i];
|
if (channel->type->copy)
|
channel = channel->type->copy(channel);
|
if (!channel) {
|
rc = -ENOMEM;
|
goto out;
|
}
|
other_channel[i] = channel;
|
}
|
|
/* Swap entry counts and channel pointers */
|
old_rxq_entries = efx->rxq_entries;
|
old_txq_entries = efx->txq_entries;
|
efx->rxq_entries = rxq_entries;
|
efx->txq_entries = txq_entries;
|
for (i = 0; i < efx->n_channels; i++)
|
swap(efx->channel[i], other_channel[i]);
|
|
/* Restart buffer table allocation */
|
efx->next_buffer_table = next_buffer_table;
|
|
for (i = 0; i < efx->n_channels; i++) {
|
channel = efx->channel[i];
|
if (!channel->type->copy)
|
continue;
|
rc = efx_probe_channel(channel);
|
if (rc)
|
goto rollback;
|
efx_init_napi_channel(efx->channel[i]);
|
}
|
|
out:
|
efx->ptp_data = NULL;
|
/* Destroy unused channel structures */
|
for (i = 0; i < efx->n_channels; i++) {
|
channel = other_channel[i];
|
if (channel && channel->type->copy) {
|
efx_fini_napi_channel(channel);
|
efx_remove_channel(channel);
|
kfree(channel);
|
}
|
}
|
|
efx->ptp_data = ptp_data;
|
rc2 = efx_soft_enable_interrupts(efx);
|
if (rc2) {
|
rc = rc ? rc : rc2;
|
netif_err(efx, drv, efx->net_dev,
|
"unable to restart interrupts on channel reallocation\n");
|
efx_schedule_reset(efx, RESET_TYPE_DISABLE);
|
} else {
|
efx_start_all(efx);
|
efx_device_attach_if_not_resetting(efx);
|
}
|
return rc;
|
|
rollback:
|
/* Swap back */
|
efx->rxq_entries = old_rxq_entries;
|
efx->txq_entries = old_txq_entries;
|
for (i = 0; i < efx->n_channels; i++)
|
swap(efx->channel[i], other_channel[i]);
|
efx_ptp_update_channel(efx, ptp_channel);
|
goto out;
|
}
|
|
int efx_set_channels(struct efx_nic *efx)
|
{
|
struct efx_tx_queue *tx_queue;
|
struct efx_channel *channel;
|
unsigned int next_queue = 0;
|
int xdp_queue_number;
|
int rc;
|
|
if (efx->xdp_tx_queue_count) {
|
EFX_WARN_ON_PARANOID(efx->xdp_tx_queues);
|
|
/* Allocate array for XDP TX queue lookup. */
|
efx->xdp_tx_queues = kcalloc(efx->xdp_tx_queue_count,
|
sizeof(*efx->xdp_tx_queues),
|
GFP_KERNEL);
|
if (!efx->xdp_tx_queues)
|
return -ENOMEM;
|
}
|
|
/* We need to mark which channels really have RX and TX
|
* queues, and adjust the TX queue numbers if we have separate
|
* RX-only and TX-only channels.
|
*/
|
xdp_queue_number = 0;
|
efx_for_each_channel(channel, efx) {
|
if (channel->channel < efx->n_rx_channels)
|
channel->rx_queue.core_index = channel->channel;
|
else
|
channel->rx_queue.core_index = -1;
|
|
if (channel->channel >= efx->tx_channel_offset) {
|
if (efx_channel_is_xdp_tx(channel)) {
|
efx_for_each_channel_tx_queue(tx_queue, channel) {
|
tx_queue->queue = next_queue++;
|
|
/* We may have a few left-over XDP TX
|
* queues owing to xdp_tx_queue_count
|
* not dividing evenly by EFX_MAX_TXQ_PER_CHANNEL.
|
* We still allocate and probe those
|
* TXQs, but never use them.
|
*/
|
if (xdp_queue_number < efx->xdp_tx_queue_count) {
|
netif_dbg(efx, drv, efx->net_dev, "Channel %u TXQ %u is XDP %u, HW %u\n",
|
channel->channel, tx_queue->label,
|
xdp_queue_number, tx_queue->queue);
|
efx->xdp_tx_queues[xdp_queue_number] = tx_queue;
|
xdp_queue_number++;
|
}
|
}
|
} else {
|
efx_for_each_channel_tx_queue(tx_queue, channel) {
|
tx_queue->queue = next_queue++;
|
netif_dbg(efx, drv, efx->net_dev, "Channel %u TXQ %u is HW %u\n",
|
channel->channel, tx_queue->label,
|
tx_queue->queue);
|
}
|
}
|
}
|
}
|
WARN_ON(xdp_queue_number != efx->xdp_tx_queue_count);
|
|
rc = netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
|
if (rc)
|
return rc;
|
return netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
|
}
|
|
bool efx_default_channel_want_txqs(struct efx_channel *channel)
|
{
|
return channel->channel - channel->efx->tx_channel_offset <
|
channel->efx->n_tx_channels;
|
}
|
|
/*************
|
* START/STOP
|
*************/
|
|
int efx_soft_enable_interrupts(struct efx_nic *efx)
|
{
|
struct efx_channel *channel, *end_channel;
|
int rc;
|
|
BUG_ON(efx->state == STATE_DISABLED);
|
|
efx->irq_soft_enabled = true;
|
smp_wmb();
|
|
efx_for_each_channel(channel, efx) {
|
if (!channel->type->keep_eventq) {
|
rc = efx_init_eventq(channel);
|
if (rc)
|
goto fail;
|
}
|
efx_start_eventq(channel);
|
}
|
|
efx_mcdi_mode_event(efx);
|
|
return 0;
|
fail:
|
end_channel = channel;
|
efx_for_each_channel(channel, efx) {
|
if (channel == end_channel)
|
break;
|
efx_stop_eventq(channel);
|
if (!channel->type->keep_eventq)
|
efx_fini_eventq(channel);
|
}
|
|
return rc;
|
}
|
|
void efx_soft_disable_interrupts(struct efx_nic *efx)
|
{
|
struct efx_channel *channel;
|
|
if (efx->state == STATE_DISABLED)
|
return;
|
|
efx_mcdi_mode_poll(efx);
|
|
efx->irq_soft_enabled = false;
|
smp_wmb();
|
|
if (efx->legacy_irq)
|
synchronize_irq(efx->legacy_irq);
|
|
efx_for_each_channel(channel, efx) {
|
if (channel->irq)
|
synchronize_irq(channel->irq);
|
|
efx_stop_eventq(channel);
|
if (!channel->type->keep_eventq)
|
efx_fini_eventq(channel);
|
}
|
|
/* Flush the asynchronous MCDI request queue */
|
efx_mcdi_flush_async(efx);
|
}
|
|
int efx_enable_interrupts(struct efx_nic *efx)
|
{
|
struct efx_channel *channel, *end_channel;
|
int rc;
|
|
/* TODO: Is this really a bug? */
|
BUG_ON(efx->state == STATE_DISABLED);
|
|
if (efx->eeh_disabled_legacy_irq) {
|
enable_irq(efx->legacy_irq);
|
efx->eeh_disabled_legacy_irq = false;
|
}
|
|
efx->type->irq_enable_master(efx);
|
|
efx_for_each_channel(channel, efx) {
|
if (channel->type->keep_eventq) {
|
rc = efx_init_eventq(channel);
|
if (rc)
|
goto fail;
|
}
|
}
|
|
rc = efx_soft_enable_interrupts(efx);
|
if (rc)
|
goto fail;
|
|
return 0;
|
|
fail:
|
end_channel = channel;
|
efx_for_each_channel(channel, efx) {
|
if (channel == end_channel)
|
break;
|
if (channel->type->keep_eventq)
|
efx_fini_eventq(channel);
|
}
|
|
efx->type->irq_disable_non_ev(efx);
|
|
return rc;
|
}
|
|
void efx_disable_interrupts(struct efx_nic *efx)
|
{
|
struct efx_channel *channel;
|
|
efx_soft_disable_interrupts(efx);
|
|
efx_for_each_channel(channel, efx) {
|
if (channel->type->keep_eventq)
|
efx_fini_eventq(channel);
|
}
|
|
efx->type->irq_disable_non_ev(efx);
|
}
|
|
void efx_start_channels(struct efx_nic *efx)
|
{
|
struct efx_tx_queue *tx_queue;
|
struct efx_rx_queue *rx_queue;
|
struct efx_channel *channel;
|
|
efx_for_each_channel(channel, efx) {
|
efx_for_each_channel_tx_queue(tx_queue, channel) {
|
efx_init_tx_queue(tx_queue);
|
atomic_inc(&efx->active_queues);
|
}
|
|
efx_for_each_channel_rx_queue(rx_queue, channel) {
|
efx_init_rx_queue(rx_queue);
|
atomic_inc(&efx->active_queues);
|
efx_stop_eventq(channel);
|
efx_fast_push_rx_descriptors(rx_queue, false);
|
efx_start_eventq(channel);
|
}
|
|
WARN_ON(channel->rx_pkt_n_frags);
|
}
|
}
|
|
void efx_stop_channels(struct efx_nic *efx)
|
{
|
struct efx_tx_queue *tx_queue;
|
struct efx_rx_queue *rx_queue;
|
struct efx_channel *channel;
|
int rc = 0;
|
|
/* Stop RX refill */
|
efx_for_each_channel(channel, efx) {
|
efx_for_each_channel_rx_queue(rx_queue, channel)
|
rx_queue->refill_enabled = false;
|
}
|
|
efx_for_each_channel(channel, efx) {
|
/* RX packet processing is pipelined, so wait for the
|
* NAPI handler to complete. At least event queue 0
|
* might be kept active by non-data events, so don't
|
* use napi_synchronize() but actually disable NAPI
|
* temporarily.
|
*/
|
if (efx_channel_has_rx_queue(channel)) {
|
efx_stop_eventq(channel);
|
efx_start_eventq(channel);
|
}
|
}
|
|
if (efx->type->fini_dmaq)
|
rc = efx->type->fini_dmaq(efx);
|
|
if (rc) {
|
netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
|
} else {
|
netif_dbg(efx, drv, efx->net_dev,
|
"successfully flushed all queues\n");
|
}
|
|
efx_for_each_channel(channel, efx) {
|
efx_for_each_channel_rx_queue(rx_queue, channel)
|
efx_fini_rx_queue(rx_queue);
|
efx_for_each_channel_tx_queue(tx_queue, channel)
|
efx_fini_tx_queue(tx_queue);
|
}
|
}
|
|
/**************************************************************************
|
*
|
* NAPI interface
|
*
|
*************************************************************************/
|
|
/* Process channel's event queue
|
*
|
* This function is responsible for processing the event queue of a
|
* single channel. The caller must guarantee that this function will
|
* never be concurrently called more than once on the same channel,
|
* though different channels may be being processed concurrently.
|
*/
|
static int efx_process_channel(struct efx_channel *channel, int budget)
|
{
|
struct efx_tx_queue *tx_queue;
|
struct list_head rx_list;
|
int spent;
|
|
if (unlikely(!channel->enabled))
|
return 0;
|
|
/* Prepare the batch receive list */
|
EFX_WARN_ON_PARANOID(channel->rx_list != NULL);
|
INIT_LIST_HEAD(&rx_list);
|
channel->rx_list = &rx_list;
|
|
efx_for_each_channel_tx_queue(tx_queue, channel) {
|
tx_queue->pkts_compl = 0;
|
tx_queue->bytes_compl = 0;
|
}
|
|
spent = efx_nic_process_eventq(channel, budget);
|
if (spent && efx_channel_has_rx_queue(channel)) {
|
struct efx_rx_queue *rx_queue =
|
efx_channel_get_rx_queue(channel);
|
|
efx_rx_flush_packet(channel);
|
efx_fast_push_rx_descriptors(rx_queue, true);
|
}
|
|
/* Update BQL */
|
efx_for_each_channel_tx_queue(tx_queue, channel) {
|
if (tx_queue->bytes_compl) {
|
netdev_tx_completed_queue(tx_queue->core_txq,
|
tx_queue->pkts_compl,
|
tx_queue->bytes_compl);
|
}
|
}
|
|
/* Receive any packets we queued up */
|
netif_receive_skb_list(channel->rx_list);
|
channel->rx_list = NULL;
|
|
return spent;
|
}
|
|
static void efx_update_irq_mod(struct efx_nic *efx, struct efx_channel *channel)
|
{
|
int step = efx->irq_mod_step_us;
|
|
if (channel->irq_mod_score < irq_adapt_low_thresh) {
|
if (channel->irq_moderation_us > step) {
|
channel->irq_moderation_us -= step;
|
efx->type->push_irq_moderation(channel);
|
}
|
} else if (channel->irq_mod_score > irq_adapt_high_thresh) {
|
if (channel->irq_moderation_us <
|
efx->irq_rx_moderation_us) {
|
channel->irq_moderation_us += step;
|
efx->type->push_irq_moderation(channel);
|
}
|
}
|
|
channel->irq_count = 0;
|
channel->irq_mod_score = 0;
|
}
|
|
/* NAPI poll handler
|
*
|
* NAPI guarantees serialisation of polls of the same device, which
|
* provides the guarantee required by efx_process_channel().
|
*/
|
static int efx_poll(struct napi_struct *napi, int budget)
|
{
|
struct efx_channel *channel =
|
container_of(napi, struct efx_channel, napi_str);
|
struct efx_nic *efx = channel->efx;
|
#ifdef CONFIG_RFS_ACCEL
|
unsigned int time;
|
#endif
|
int spent;
|
|
netif_vdbg(efx, intr, efx->net_dev,
|
"channel %d NAPI poll executing on CPU %d\n",
|
channel->channel, raw_smp_processor_id());
|
|
spent = efx_process_channel(channel, budget);
|
|
xdp_do_flush_map();
|
|
if (spent < budget) {
|
if (efx_channel_has_rx_queue(channel) &&
|
efx->irq_rx_adaptive &&
|
unlikely(++channel->irq_count == 1000)) {
|
efx_update_irq_mod(efx, channel);
|
}
|
|
#ifdef CONFIG_RFS_ACCEL
|
/* Perhaps expire some ARFS filters */
|
time = jiffies - channel->rfs_last_expiry;
|
/* Would our quota be >= 20? */
|
if (channel->rfs_filter_count * time >= 600 * HZ)
|
mod_delayed_work(system_wq, &channel->filter_work, 0);
|
#endif
|
|
/* There is no race here; although napi_disable() will
|
* only wait for napi_complete(), this isn't a problem
|
* since efx_nic_eventq_read_ack() will have no effect if
|
* interrupts have already been disabled.
|
*/
|
if (napi_complete_done(napi, spent))
|
efx_nic_eventq_read_ack(channel);
|
}
|
|
return spent;
|
}
|
|
void efx_init_napi_channel(struct efx_channel *channel)
|
{
|
struct efx_nic *efx = channel->efx;
|
|
channel->napi_dev = efx->net_dev;
|
netif_napi_add(channel->napi_dev, &channel->napi_str,
|
efx_poll, napi_weight);
|
}
|
|
void efx_init_napi(struct efx_nic *efx)
|
{
|
struct efx_channel *channel;
|
|
efx_for_each_channel(channel, efx)
|
efx_init_napi_channel(channel);
|
}
|
|
void efx_fini_napi_channel(struct efx_channel *channel)
|
{
|
if (channel->napi_dev)
|
netif_napi_del(&channel->napi_str);
|
|
channel->napi_dev = NULL;
|
}
|
|
void efx_fini_napi(struct efx_nic *efx)
|
{
|
struct efx_channel *channel;
|
|
efx_for_each_channel(channel, efx)
|
efx_fini_napi_channel(channel);
|
}
|
