// SPDX-License-Identifier: GPL-2.0-only
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/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2005-2019 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include "net_driver.h"
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#include "ef100_rx.h"
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#include "rx_common.h"
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#include "efx.h"
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#include "nic_common.h"
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#include "mcdi_functions.h"
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#include "ef100_regs.h"
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#include "ef100_nic.h"
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#include "io.h"
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/* Get the value of a field in the RX prefix */
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#define PREFIX_OFFSET_W(_f) (ESF_GZ_RX_PREFIX_ ## _f ## _LBN / 32)
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#define PREFIX_OFFSET_B(_f) (ESF_GZ_RX_PREFIX_ ## _f ## _LBN % 32)
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#define PREFIX_WIDTH_MASK(_f) ((1UL << ESF_GZ_RX_PREFIX_ ## _f ## _WIDTH) - 1)
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#define PREFIX_WORD(_p, _f) le32_to_cpu((__force __le32)(_p)[PREFIX_OFFSET_W(_f)])
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#define PREFIX_FIELD(_p, _f) ((PREFIX_WORD(_p, _f) >> PREFIX_OFFSET_B(_f)) & \
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PREFIX_WIDTH_MASK(_f))
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#define ESF_GZ_RX_PREFIX_NT_OR_INNER_L3_CLASS_LBN \
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(ESF_GZ_RX_PREFIX_CLASS_LBN + ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_LBN)
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#define ESF_GZ_RX_PREFIX_NT_OR_INNER_L3_CLASS_WIDTH \
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ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_WIDTH
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bool ef100_rx_buf_hash_valid(const u8 *prefix)
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{
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return PREFIX_FIELD(prefix, RSS_HASH_VALID);
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}
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static bool ef100_has_fcs_error(struct efx_channel *channel, u32 *prefix)
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{
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u16 rxclass;
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u8 l2status;
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rxclass = le16_to_cpu((__force __le16)PREFIX_FIELD(prefix, CLASS));
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l2status = PREFIX_FIELD(&rxclass, HCLASS_L2_STATUS);
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if (likely(l2status == ESE_GZ_RH_HCLASS_L2_STATUS_OK))
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/* Everything is ok */
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return false;
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if (l2status == ESE_GZ_RH_HCLASS_L2_STATUS_FCS_ERR)
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channel->n_rx_eth_crc_err++;
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return true;
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}
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void __ef100_rx_packet(struct efx_channel *channel)
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{
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struct efx_rx_buffer *rx_buf = efx_rx_buffer(&channel->rx_queue, channel->rx_pkt_index);
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struct efx_nic *efx = channel->efx;
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u8 *eh = efx_rx_buf_va(rx_buf);
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__wsum csum = 0;
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u32 *prefix;
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prefix = (u32 *)(eh - ESE_GZ_RX_PKT_PREFIX_LEN);
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if (ef100_has_fcs_error(channel, prefix) &&
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unlikely(!(efx->net_dev->features & NETIF_F_RXALL)))
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goto out;
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rx_buf->len = le16_to_cpu((__force __le16)PREFIX_FIELD(prefix, LENGTH));
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if (rx_buf->len <= sizeof(struct ethhdr)) {
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if (net_ratelimit())
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netif_err(channel->efx, rx_err, channel->efx->net_dev,
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"RX packet too small (%d)\n", rx_buf->len);
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++channel->n_rx_frm_trunc;
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goto out;
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}
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if (likely(efx->net_dev->features & NETIF_F_RXCSUM)) {
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if (PREFIX_FIELD(prefix, NT_OR_INNER_L3_CLASS) == 1) {
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++channel->n_rx_ip_hdr_chksum_err;
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} else {
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u16 sum = be16_to_cpu((__force __be16)PREFIX_FIELD(prefix, CSUM_FRAME));
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csum = (__force __wsum) sum;
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}
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}
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if (channel->type->receive_skb) {
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struct efx_rx_queue *rx_queue =
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efx_channel_get_rx_queue(channel);
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/* no support for special channels yet, so just discard */
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WARN_ON_ONCE(1);
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efx_free_rx_buffers(rx_queue, rx_buf, 1);
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goto out;
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}
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efx_rx_packet_gro(channel, rx_buf, channel->rx_pkt_n_frags, eh, csum);
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out:
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channel->rx_pkt_n_frags = 0;
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}
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static void ef100_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index)
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{
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struct efx_rx_buffer *rx_buf = efx_rx_buffer(rx_queue, index);
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struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
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struct efx_nic *efx = rx_queue->efx;
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++rx_queue->rx_packets;
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netif_vdbg(efx, rx_status, efx->net_dev,
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"RX queue %d received id %x\n",
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efx_rx_queue_index(rx_queue), index);
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efx_sync_rx_buffer(efx, rx_buf, efx->rx_dma_len);
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prefetch(efx_rx_buf_va(rx_buf));
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rx_buf->page_offset += efx->rx_prefix_size;
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efx_recycle_rx_pages(channel, rx_buf, 1);
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efx_rx_flush_packet(channel);
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channel->rx_pkt_n_frags = 1;
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channel->rx_pkt_index = index;
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}
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void efx_ef100_ev_rx(struct efx_channel *channel, const efx_qword_t *p_event)
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{
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struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
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unsigned int n_packets =
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EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_NUM_PKT);
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int i;
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WARN_ON_ONCE(!n_packets);
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if (n_packets > 1)
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++channel->n_rx_merge_events;
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channel->irq_mod_score += 2 * n_packets;
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for (i = 0; i < n_packets; ++i) {
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ef100_rx_packet(rx_queue,
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rx_queue->removed_count & rx_queue->ptr_mask);
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++rx_queue->removed_count;
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}
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}
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void ef100_rx_write(struct efx_rx_queue *rx_queue)
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{
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struct efx_rx_buffer *rx_buf;
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unsigned int idx;
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efx_qword_t *rxd;
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efx_dword_t rxdb;
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while (rx_queue->notified_count != rx_queue->added_count) {
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idx = rx_queue->notified_count & rx_queue->ptr_mask;
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rx_buf = efx_rx_buffer(rx_queue, idx);
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rxd = efx_rx_desc(rx_queue, idx);
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EFX_POPULATE_QWORD_1(*rxd, ESF_GZ_RX_BUF_ADDR, rx_buf->dma_addr);
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++rx_queue->notified_count;
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}
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wmb();
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EFX_POPULATE_DWORD_1(rxdb, ERF_GZ_RX_RING_PIDX,
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rx_queue->added_count & rx_queue->ptr_mask);
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efx_writed_page(rx_queue->efx, &rxdb,
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ER_GZ_RX_RING_DOORBELL, efx_rx_queue_index(rx_queue));
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}
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