// SPDX-License-Identifier: GPL-2.0-only
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/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2005-2018 Solarflare Communications Inc.
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* Copyright 2019-2020 Xilinx Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include "net_driver.h"
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#include <linux/module.h>
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#include <linux/aer.h>
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#include "efx_common.h"
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#include "efx_channels.h"
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#include "io.h"
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#include "ef100_nic.h"
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#include "ef100_netdev.h"
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#include "ef100_regs.h"
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#include "ef100.h"
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#define EFX_EF100_PCI_DEFAULT_BAR 2
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/* Number of bytes at start of vendor specified extended capability that indicate
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* that the capability is vendor specified. i.e. offset from value returned by
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* pci_find_next_ext_capability() to beginning of vendor specified capability
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* header.
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*/
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#define PCI_EXT_CAP_HDR_LENGTH 4
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/* Expected size of a Xilinx continuation address table entry. */
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#define ESE_GZ_CFGBAR_CONT_CAP_MIN_LENGTH 16
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struct ef100_func_ctl_window {
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bool valid;
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unsigned int bar;
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u64 offset;
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};
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static int ef100_pci_walk_xilinx_table(struct efx_nic *efx, u64 offset,
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struct ef100_func_ctl_window *result);
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/* Number of bytes to offset when reading bit position x with dword accessors. */
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#define ROUND_DOWN_TO_DWORD(x) (((x) & (~31)) >> 3)
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#define EXTRACT_BITS(x, lbn, width) \
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(((x) >> ((lbn) & 31)) & ((1ull << (width)) - 1))
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static u32 _ef100_pci_get_bar_bits_with_width(struct efx_nic *efx,
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int structure_start,
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int lbn, int width)
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{
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efx_dword_t dword;
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efx_readd(efx, &dword, structure_start + ROUND_DOWN_TO_DWORD(lbn));
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return EXTRACT_BITS(le32_to_cpu(dword.u32[0]), lbn, width);
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}
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#define ef100_pci_get_bar_bits(efx, entry_location, bitdef) \
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_ef100_pci_get_bar_bits_with_width(efx, entry_location, \
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ESF_GZ_CFGBAR_ ## bitdef ## _LBN, \
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ESF_GZ_CFGBAR_ ## bitdef ## _WIDTH)
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static int ef100_pci_parse_ef100_entry(struct efx_nic *efx, int entry_location,
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struct ef100_func_ctl_window *result)
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{
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u64 offset = ef100_pci_get_bar_bits(efx, entry_location, EF100_FUNC_CTL_WIN_OFF) <<
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ESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT;
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u32 bar = ef100_pci_get_bar_bits(efx, entry_location, EF100_BAR);
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netif_dbg(efx, probe, efx->net_dev,
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"Found EF100 function control window bar=%d offset=0x%llx\n",
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bar, offset);
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if (result->valid) {
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netif_err(efx, probe, efx->net_dev,
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"Duplicated EF100 table entry.\n");
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return -EINVAL;
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}
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if (bar == ESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM ||
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bar == ESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID) {
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netif_err(efx, probe, efx->net_dev,
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"Bad BAR value of %d in Xilinx capabilities EF100 entry.\n",
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bar);
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return -EINVAL;
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}
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result->bar = bar;
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result->offset = offset;
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result->valid = true;
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return 0;
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}
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static bool ef100_pci_does_bar_overflow(struct efx_nic *efx, int bar,
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u64 next_entry)
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{
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return next_entry + ESE_GZ_CFGBAR_ENTRY_HEADER_SIZE >
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pci_resource_len(efx->pci_dev, bar);
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}
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/* Parse a Xilinx capabilities table entry describing a continuation to a new
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* sub-table.
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*/
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static int ef100_pci_parse_continue_entry(struct efx_nic *efx, int entry_location,
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struct ef100_func_ctl_window *result)
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{
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unsigned int previous_bar;
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efx_oword_t entry;
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u64 offset;
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int rc = 0;
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u32 bar;
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efx_reado(efx, &entry, entry_location);
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bar = EFX_OWORD_FIELD32(entry, ESF_GZ_CFGBAR_CONT_CAP_BAR);
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offset = EFX_OWORD_FIELD64(entry, ESF_GZ_CFGBAR_CONT_CAP_OFFSET) <<
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ESE_GZ_CONT_CAP_OFFSET_BYTES_SHIFT;
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previous_bar = efx->mem_bar;
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if (bar == ESE_GZ_VSEC_BAR_NUM_EXPANSION_ROM ||
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bar == ESE_GZ_VSEC_BAR_NUM_INVALID) {
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netif_err(efx, probe, efx->net_dev,
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"Bad BAR value of %d in Xilinx capabilities sub-table.\n",
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bar);
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return -EINVAL;
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}
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if (bar != previous_bar) {
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efx_fini_io(efx);
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if (ef100_pci_does_bar_overflow(efx, bar, offset)) {
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netif_err(efx, probe, efx->net_dev,
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"Xilinx table will overrun BAR[%d] offset=0x%llx\n",
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bar, offset);
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return -EINVAL;
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}
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/* Temporarily map new BAR. */
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rc = efx_init_io(efx, bar,
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(dma_addr_t)DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH),
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pci_resource_len(efx->pci_dev, bar));
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if (rc) {
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netif_err(efx, probe, efx->net_dev,
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"Mapping new BAR for Xilinx table failed, rc=%d\n", rc);
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return rc;
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}
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}
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rc = ef100_pci_walk_xilinx_table(efx, offset, result);
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if (rc)
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return rc;
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if (bar != previous_bar) {
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efx_fini_io(efx);
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/* Put old BAR back. */
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rc = efx_init_io(efx, previous_bar,
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(dma_addr_t)DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH),
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pci_resource_len(efx->pci_dev, previous_bar));
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if (rc) {
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netif_err(efx, probe, efx->net_dev,
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"Putting old BAR back failed, rc=%d\n", rc);
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return rc;
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}
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}
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return 0;
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}
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/* Iterate over the Xilinx capabilities table in the currently mapped BAR and
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* call ef100_pci_parse_ef100_entry() on any EF100 entries and
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* ef100_pci_parse_continue_entry() on any table continuations.
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*/
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static int ef100_pci_walk_xilinx_table(struct efx_nic *efx, u64 offset,
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struct ef100_func_ctl_window *result)
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{
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u64 current_entry = offset;
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int rc = 0;
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while (true) {
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u32 id = ef100_pci_get_bar_bits(efx, current_entry, ENTRY_FORMAT);
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u32 last = ef100_pci_get_bar_bits(efx, current_entry, ENTRY_LAST);
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u32 rev = ef100_pci_get_bar_bits(efx, current_entry, ENTRY_REV);
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u32 entry_size;
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if (id == ESE_GZ_CFGBAR_ENTRY_LAST)
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return 0;
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entry_size = ef100_pci_get_bar_bits(efx, current_entry, ENTRY_SIZE);
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netif_dbg(efx, probe, efx->net_dev,
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"Seen Xilinx table entry 0x%x size 0x%x at 0x%llx in BAR[%d]\n",
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id, entry_size, current_entry, efx->mem_bar);
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if (entry_size < sizeof(u32) * 2) {
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netif_err(efx, probe, efx->net_dev,
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"Xilinx table entry too short len=0x%x\n", entry_size);
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return -EINVAL;
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}
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switch (id) {
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case ESE_GZ_CFGBAR_ENTRY_EF100:
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if (rev != ESE_GZ_CFGBAR_ENTRY_REV_EF100 ||
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entry_size < ESE_GZ_CFGBAR_ENTRY_SIZE_EF100) {
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netif_err(efx, probe, efx->net_dev,
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"Bad length or rev for EF100 entry in Xilinx capabilities table. entry_size=%d rev=%d.\n",
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entry_size, rev);
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return -EINVAL;
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}
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rc = ef100_pci_parse_ef100_entry(efx, current_entry,
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result);
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if (rc)
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return rc;
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break;
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case ESE_GZ_CFGBAR_ENTRY_CONT_CAP_ADDR:
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if (rev != 0 || entry_size < ESE_GZ_CFGBAR_CONT_CAP_MIN_LENGTH) {
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netif_err(efx, probe, efx->net_dev,
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"Bad length or rev for continue entry in Xilinx capabilities table. entry_size=%d rev=%d.\n",
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entry_size, rev);
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return -EINVAL;
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}
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rc = ef100_pci_parse_continue_entry(efx, current_entry, result);
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if (rc)
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return rc;
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break;
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default:
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/* Ignore unknown table entries. */
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break;
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}
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if (last)
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return 0;
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current_entry += entry_size;
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if (ef100_pci_does_bar_overflow(efx, efx->mem_bar, current_entry)) {
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netif_err(efx, probe, efx->net_dev,
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"Xilinx table overrun at position=0x%llx.\n",
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current_entry);
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return -EINVAL;
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}
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}
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}
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static int _ef100_pci_get_config_bits_with_width(struct efx_nic *efx,
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int structure_start, int lbn,
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int width, u32 *result)
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{
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int rc, pos = structure_start + ROUND_DOWN_TO_DWORD(lbn);
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u32 temp;
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rc = pci_read_config_dword(efx->pci_dev, pos, &temp);
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if (rc) {
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netif_err(efx, probe, efx->net_dev,
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"Failed to read PCI config dword at %d\n",
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pos);
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return rc;
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}
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*result = EXTRACT_BITS(temp, lbn, width);
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return 0;
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}
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#define ef100_pci_get_config_bits(efx, entry_location, bitdef, result) \
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_ef100_pci_get_config_bits_with_width(efx, entry_location, \
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ESF_GZ_VSEC_ ## bitdef ## _LBN, \
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ESF_GZ_VSEC_ ## bitdef ## _WIDTH, result)
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/* Call ef100_pci_walk_xilinx_table() for the Xilinx capabilities table pointed
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* to by this PCI_EXT_CAP_ID_VNDR.
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*/
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static int ef100_pci_parse_xilinx_cap(struct efx_nic *efx, int vndr_cap,
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bool has_offset_hi,
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struct ef100_func_ctl_window *result)
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{
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u32 offset_high = 0;
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u32 offset_lo = 0;
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u64 offset = 0;
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u32 bar = 0;
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int rc = 0;
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rc = ef100_pci_get_config_bits(efx, vndr_cap, TBL_BAR, &bar);
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if (rc) {
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netif_err(efx, probe, efx->net_dev,
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"Failed to read ESF_GZ_VSEC_TBL_BAR, rc=%d\n",
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rc);
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return rc;
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}
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if (bar == ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_EXPANSION_ROM ||
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bar == ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_INVALID) {
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netif_err(efx, probe, efx->net_dev,
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"Bad BAR value of %d in Xilinx capabilities sub-table.\n",
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bar);
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return -EINVAL;
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}
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rc = ef100_pci_get_config_bits(efx, vndr_cap, TBL_OFF_LO, &offset_lo);
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if (rc) {
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netif_err(efx, probe, efx->net_dev,
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"Failed to read ESF_GZ_VSEC_TBL_OFF_LO, rc=%d\n",
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rc);
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return rc;
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}
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/* Get optional extension to 64bit offset. */
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if (has_offset_hi) {
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rc = ef100_pci_get_config_bits(efx, vndr_cap, TBL_OFF_HI, &offset_high);
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if (rc) {
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netif_err(efx, probe, efx->net_dev,
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"Failed to read ESF_GZ_VSEC_TBL_OFF_HI, rc=%d\n",
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rc);
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return rc;
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}
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}
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offset = (((u64)offset_lo) << ESE_GZ_VSEC_TBL_OFF_LO_BYTES_SHIFT) |
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(((u64)offset_high) << ESE_GZ_VSEC_TBL_OFF_HI_BYTES_SHIFT);
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if (offset > pci_resource_len(efx->pci_dev, bar) - sizeof(u32) * 2) {
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netif_err(efx, probe, efx->net_dev,
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"Xilinx table will overrun BAR[%d] offset=0x%llx\n",
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bar, offset);
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return -EINVAL;
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}
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/* Temporarily map BAR. */
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rc = efx_init_io(efx, bar,
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(dma_addr_t)DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH),
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pci_resource_len(efx->pci_dev, bar));
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if (rc) {
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netif_err(efx, probe, efx->net_dev,
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"efx_init_io failed, rc=%d\n", rc);
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return rc;
|
}
|
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rc = ef100_pci_walk_xilinx_table(efx, offset, result);
|
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/* Unmap temporarily mapped BAR. */
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efx_fini_io(efx);
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return rc;
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}
|
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/* Call ef100_pci_parse_ef100_entry() for each Xilinx PCI_EXT_CAP_ID_VNDR
|
* capability.
|
*/
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static int ef100_pci_find_func_ctrl_window(struct efx_nic *efx,
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struct ef100_func_ctl_window *result)
|
{
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int num_xilinx_caps = 0;
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int cap = 0;
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result->valid = false;
|
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while ((cap = pci_find_next_ext_capability(efx->pci_dev, cap, PCI_EXT_CAP_ID_VNDR)) != 0) {
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int vndr_cap = cap + PCI_EXT_CAP_HDR_LENGTH;
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u32 vsec_ver = 0;
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u32 vsec_len = 0;
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u32 vsec_id = 0;
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int rc = 0;
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num_xilinx_caps++;
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rc = ef100_pci_get_config_bits(efx, vndr_cap, ID, &vsec_id);
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if (rc) {
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netif_err(efx, probe, efx->net_dev,
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"Failed to read ESF_GZ_VSEC_ID, rc=%d\n",
|
rc);
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return rc;
|
}
|
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rc = ef100_pci_get_config_bits(efx, vndr_cap, VER, &vsec_ver);
|
if (rc) {
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netif_err(efx, probe, efx->net_dev,
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"Failed to read ESF_GZ_VSEC_VER, rc=%d\n",
|
rc);
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return rc;
|
}
|
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/* Get length of whole capability - i.e. starting at cap */
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rc = ef100_pci_get_config_bits(efx, vndr_cap, LEN, &vsec_len);
|
if (rc) {
|
netif_err(efx, probe, efx->net_dev,
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"Failed to read ESF_GZ_VSEC_LEN, rc=%d\n",
|
rc);
|
return rc;
|
}
|
|
if (vsec_id == ESE_GZ_XILINX_VSEC_ID &&
|
vsec_ver == ESE_GZ_VSEC_VER_XIL_CFGBAR &&
|
vsec_len >= ESE_GZ_VSEC_LEN_MIN) {
|
bool has_offset_hi = (vsec_len >= ESE_GZ_VSEC_LEN_HIGH_OFFT);
|
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rc = ef100_pci_parse_xilinx_cap(efx, vndr_cap,
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has_offset_hi, result);
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if (rc)
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return rc;
|
}
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}
|
|
if (num_xilinx_caps && !result->valid) {
|
netif_err(efx, probe, efx->net_dev,
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"Seen %d Xilinx tables, but no EF100 entry.\n",
|
num_xilinx_caps);
|
return -EINVAL;
|
}
|
|
return 0;
|
}
|
|
/* Final NIC shutdown
|
* This is called only at module unload (or hotplug removal). A PF can call
|
* this on its VFs to ensure they are unbound first.
|
*/
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static void ef100_pci_remove(struct pci_dev *pci_dev)
|
{
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struct efx_nic *efx;
|
|
efx = pci_get_drvdata(pci_dev);
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if (!efx)
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return;
|
|
rtnl_lock();
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dev_close(efx->net_dev);
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rtnl_unlock();
|
|
/* Unregistering our netdev notifier triggers unbinding of TC indirect
|
* blocks, so we have to do it before PCI removal.
|
*/
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unregister_netdevice_notifier(&efx->netdev_notifier);
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ef100_remove(efx);
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efx_fini_io(efx);
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netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
|
|
pci_set_drvdata(pci_dev, NULL);
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efx_fini_struct(efx);
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free_netdev(efx->net_dev);
|
|
pci_disable_pcie_error_reporting(pci_dev);
|
};
|
|
static int ef100_pci_probe(struct pci_dev *pci_dev,
|
const struct pci_device_id *entry)
|
{
|
struct ef100_func_ctl_window fcw = { 0 };
|
struct net_device *net_dev;
|
struct efx_nic *efx;
|
int rc;
|
|
/* Allocate and initialise a struct net_device and struct efx_nic */
|
net_dev = alloc_etherdev_mq(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES);
|
if (!net_dev)
|
return -ENOMEM;
|
efx = netdev_priv(net_dev);
|
efx->type = (const struct efx_nic_type *)entry->driver_data;
|
|
pci_set_drvdata(pci_dev, efx);
|
SET_NETDEV_DEV(net_dev, &pci_dev->dev);
|
rc = efx_init_struct(efx, pci_dev, net_dev);
|
if (rc)
|
goto fail;
|
|
efx->vi_stride = EF100_DEFAULT_VI_STRIDE;
|
netif_info(efx, probe, efx->net_dev,
|
"Solarflare EF100 NIC detected\n");
|
|
rc = ef100_pci_find_func_ctrl_window(efx, &fcw);
|
if (rc) {
|
netif_err(efx, probe, efx->net_dev,
|
"Error looking for ef100 function control window, rc=%d\n",
|
rc);
|
goto fail;
|
}
|
|
if (!fcw.valid) {
|
/* Extended capability not found - use defaults. */
|
fcw.bar = EFX_EF100_PCI_DEFAULT_BAR;
|
fcw.offset = 0;
|
fcw.valid = true;
|
}
|
|
if (fcw.offset > pci_resource_len(efx->pci_dev, fcw.bar) - ESE_GZ_FCW_LEN) {
|
netif_err(efx, probe, efx->net_dev,
|
"Func control window overruns BAR\n");
|
rc = -EIO;
|
goto fail;
|
}
|
|
/* Set up basic I/O (BAR mappings etc) */
|
rc = efx_init_io(efx, fcw.bar,
|
(dma_addr_t)DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH),
|
pci_resource_len(efx->pci_dev, fcw.bar));
|
if (rc)
|
goto fail;
|
|
efx->reg_base = fcw.offset;
|
|
efx->netdev_notifier.notifier_call = ef100_netdev_event;
|
rc = register_netdevice_notifier(&efx->netdev_notifier);
|
if (rc) {
|
netif_err(efx, probe, efx->net_dev,
|
"Failed to register netdevice notifier, rc=%d\n", rc);
|
goto fail;
|
}
|
|
rc = efx->type->probe(efx);
|
if (rc)
|
goto fail;
|
|
netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
|
|
return 0;
|
|
fail:
|
ef100_pci_remove(pci_dev);
|
return rc;
|
}
|
|
/* PCI device ID table */
|
static const struct pci_device_id ef100_pci_table[] = {
|
{PCI_DEVICE(PCI_VENDOR_ID_XILINX, 0x0100), /* Riverhead PF */
|
.driver_data = (unsigned long) &ef100_pf_nic_type },
|
{PCI_DEVICE(PCI_VENDOR_ID_XILINX, 0x1100), /* Riverhead VF */
|
.driver_data = (unsigned long) &ef100_vf_nic_type },
|
{0} /* end of list */
|
};
|
|
struct pci_driver ef100_pci_driver = {
|
.name = "sfc_ef100",
|
.id_table = ef100_pci_table,
|
.probe = ef100_pci_probe,
|
.remove = ef100_pci_remove,
|
.err_handler = &efx_err_handlers,
|
};
|
|
MODULE_DEVICE_TABLE(pci, ef100_pci_table);
|
