// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Microsemi Ocelot PTP clock driver
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*
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* Copyright (c) 2017 Microsemi Corporation
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* Copyright 2020 NXP
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*/
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#include <soc/mscc/ocelot_ptp.h>
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#include <soc/mscc/ocelot_sys.h>
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#include <soc/mscc/ocelot.h>
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int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts)
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{
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struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
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unsigned long flags;
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time64_t s;
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u32 val;
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s64 ns;
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spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
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val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
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val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
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val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
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ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
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s = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN) & 0xffff;
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s <<= 32;
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s += ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
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ns = ocelot_read_rix(ocelot, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
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spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
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/* Deal with negative values */
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if (ns >= 0x3ffffff0 && ns <= 0x3fffffff) {
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s--;
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ns &= 0xf;
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ns += 999999984;
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}
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set_normalized_timespec64(ts, s, ns);
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return 0;
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}
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EXPORT_SYMBOL(ocelot_ptp_gettime64);
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int ocelot_ptp_settime64(struct ptp_clock_info *ptp,
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const struct timespec64 *ts)
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{
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struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
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val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
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val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
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val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE);
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ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
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ocelot_write_rix(ocelot, lower_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_LSB,
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TOD_ACC_PIN);
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ocelot_write_rix(ocelot, upper_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_MSB,
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TOD_ACC_PIN);
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ocelot_write_rix(ocelot, ts->tv_nsec, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
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val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
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val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
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val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_LOAD);
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ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
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spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(ocelot_ptp_settime64);
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int ocelot_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) {
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struct ocelot *ocelot = container_of(ptp, struct ocelot,
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ptp_info);
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
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val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
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val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK |
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PTP_PIN_CFG_DOM);
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val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE);
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ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
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ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
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ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN);
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ocelot_write_rix(ocelot, delta, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
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val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
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val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK |
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PTP_PIN_CFG_DOM);
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val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_DELTA);
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ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
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spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
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} else {
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/* Fall back using ocelot_ptp_settime64 which is not exact. */
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struct timespec64 ts;
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u64 now;
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ocelot_ptp_gettime64(ptp, &ts);
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now = ktime_to_ns(timespec64_to_ktime(ts));
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ts = ns_to_timespec64(now + delta);
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ocelot_ptp_settime64(ptp, &ts);
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}
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return 0;
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}
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EXPORT_SYMBOL(ocelot_ptp_adjtime);
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int ocelot_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
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{
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struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
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u32 unit = 0, direction = 0;
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unsigned long flags;
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u64 adj = 0;
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spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
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if (!scaled_ppm)
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goto disable_adj;
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if (scaled_ppm < 0) {
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direction = PTP_CFG_CLK_ADJ_CFG_DIR;
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scaled_ppm = -scaled_ppm;
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}
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adj = PSEC_PER_SEC << 16;
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do_div(adj, scaled_ppm);
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do_div(adj, 1000);
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/* If the adjustment value is too large, use ns instead */
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if (adj >= (1L << 30)) {
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unit = PTP_CFG_CLK_ADJ_FREQ_NS;
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do_div(adj, 1000);
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}
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/* Still too big */
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if (adj >= (1L << 30))
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goto disable_adj;
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ocelot_write(ocelot, unit | adj, PTP_CLK_CFG_ADJ_FREQ);
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ocelot_write(ocelot, PTP_CFG_CLK_ADJ_CFG_ENA | direction,
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PTP_CLK_CFG_ADJ_CFG);
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spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
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return 0;
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disable_adj:
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ocelot_write(ocelot, 0, PTP_CLK_CFG_ADJ_CFG);
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spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(ocelot_ptp_adjfine);
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int ocelot_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
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enum ptp_pin_function func, unsigned int chan)
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{
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switch (func) {
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case PTP_PF_NONE:
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case PTP_PF_PEROUT:
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break;
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case PTP_PF_EXTTS:
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case PTP_PF_PHYSYNC:
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return -1;
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}
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return 0;
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}
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EXPORT_SYMBOL(ocelot_ptp_verify);
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int ocelot_ptp_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq, int on)
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{
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struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
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struct timespec64 ts_phase, ts_period;
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enum ocelot_ptp_pins ptp_pin;
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unsigned long flags;
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bool pps = false;
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int pin = -1;
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s64 wf_high;
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s64 wf_low;
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u32 val;
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switch (rq->type) {
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case PTP_CLK_REQ_PEROUT:
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/* Reject requests with unsupported flags */
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if (rq->perout.flags & ~(PTP_PEROUT_DUTY_CYCLE |
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PTP_PEROUT_PHASE))
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return -EOPNOTSUPP;
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pin = ptp_find_pin(ocelot->ptp_clock, PTP_PF_PEROUT,
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rq->perout.index);
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if (pin == 0)
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ptp_pin = PTP_PIN_0;
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else if (pin == 1)
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ptp_pin = PTP_PIN_1;
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else if (pin == 2)
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ptp_pin = PTP_PIN_2;
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else if (pin == 3)
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ptp_pin = PTP_PIN_3;
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else
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return -EBUSY;
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ts_period.tv_sec = rq->perout.period.sec;
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ts_period.tv_nsec = rq->perout.period.nsec;
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if (ts_period.tv_sec == 1 && ts_period.tv_nsec == 0)
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pps = true;
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/* Handle turning off */
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if (!on) {
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spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
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val = PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE);
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ocelot_write_rix(ocelot, val, PTP_PIN_CFG, ptp_pin);
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spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
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break;
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}
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if (rq->perout.flags & PTP_PEROUT_PHASE) {
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ts_phase.tv_sec = rq->perout.phase.sec;
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ts_phase.tv_nsec = rq->perout.phase.nsec;
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} else {
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/* Compatibility */
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ts_phase.tv_sec = rq->perout.start.sec;
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ts_phase.tv_nsec = rq->perout.start.nsec;
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}
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if (ts_phase.tv_sec || (ts_phase.tv_nsec && !pps)) {
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dev_warn(ocelot->dev,
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"Absolute start time not supported!\n");
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dev_warn(ocelot->dev,
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"Accept nsec for PPS phase adjustment, otherwise start time should be 0 0.\n");
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return -EINVAL;
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}
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/* Calculate waveform high and low times */
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if (rq->perout.flags & PTP_PEROUT_DUTY_CYCLE) {
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struct timespec64 ts_on;
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ts_on.tv_sec = rq->perout.on.sec;
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ts_on.tv_nsec = rq->perout.on.nsec;
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wf_high = timespec64_to_ns(&ts_on);
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} else {
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if (pps) {
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wf_high = 1000;
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} else {
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wf_high = timespec64_to_ns(&ts_period);
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wf_high = div_s64(wf_high, 2);
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}
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}
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wf_low = timespec64_to_ns(&ts_period);
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wf_low -= wf_high;
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/* Handle PPS request */
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if (pps) {
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spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
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ocelot_write_rix(ocelot, ts_phase.tv_nsec,
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PTP_PIN_WF_LOW_PERIOD, ptp_pin);
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ocelot_write_rix(ocelot, wf_high,
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PTP_PIN_WF_HIGH_PERIOD, ptp_pin);
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val = PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_CLOCK);
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val |= PTP_PIN_CFG_SYNC;
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ocelot_write_rix(ocelot, val, PTP_PIN_CFG, ptp_pin);
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spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
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break;
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}
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/* Handle periodic clock */
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if (wf_high > 0x3fffffff || wf_high <= 0x6)
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return -EINVAL;
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if (wf_low > 0x3fffffff || wf_low <= 0x6)
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return -EINVAL;
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spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
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ocelot_write_rix(ocelot, wf_low, PTP_PIN_WF_LOW_PERIOD,
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ptp_pin);
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ocelot_write_rix(ocelot, wf_high, PTP_PIN_WF_HIGH_PERIOD,
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ptp_pin);
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val = PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_CLOCK);
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ocelot_write_rix(ocelot, val, PTP_PIN_CFG, ptp_pin);
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spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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EXPORT_SYMBOL(ocelot_ptp_enable);
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int ocelot_init_timestamp(struct ocelot *ocelot,
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const struct ptp_clock_info *info)
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{
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struct ptp_clock *ptp_clock;
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int i;
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ocelot->ptp_info = *info;
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for (i = 0; i < OCELOT_PTP_PINS_NUM; i++) {
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struct ptp_pin_desc *p = &ocelot->ptp_pins[i];
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snprintf(p->name, sizeof(p->name), "switch_1588_dat%d", i);
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p->index = i;
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p->func = PTP_PF_NONE;
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}
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ocelot->ptp_info.pin_config = &ocelot->ptp_pins[0];
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ptp_clock = ptp_clock_register(&ocelot->ptp_info, ocelot->dev);
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if (IS_ERR(ptp_clock))
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return PTR_ERR(ptp_clock);
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/* Check if PHC support is missing at the configuration level */
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if (!ptp_clock)
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return 0;
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ocelot->ptp_clock = ptp_clock;
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ocelot_write(ocelot, SYS_PTP_CFG_PTP_STAMP_WID(30), SYS_PTP_CFG);
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ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_LOW);
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ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_HIGH);
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ocelot_write(ocelot, PTP_CFG_MISC_PTP_EN, PTP_CFG_MISC);
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/* There is no device reconfiguration, PTP Rx stamping is always
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* enabled.
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*/
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ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
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return 0;
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}
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EXPORT_SYMBOL(ocelot_init_timestamp);
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int ocelot_deinit_timestamp(struct ocelot *ocelot)
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{
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if (ocelot->ptp_clock)
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ptp_clock_unregister(ocelot->ptp_clock);
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return 0;
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}
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EXPORT_SYMBOL(ocelot_deinit_timestamp);
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