// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Register map access API - ENCX24J600 support
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*
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* Copyright 2015 Gridpoint
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*
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* Author: Jon Ringle <jringle@gridpoint.com>
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*/
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#include "encx24j600_hw.h"
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static int encx24j600_switch_bank(struct encx24j600_context *ctx,
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int bank)
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{
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int ret = 0;
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int bank_opcode = BANK_SELECT(bank);
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ret = spi_write(ctx->spi, &bank_opcode, 1);
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if (ret == 0)
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ctx->bank = bank;
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return ret;
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}
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static int encx24j600_cmdn(struct encx24j600_context *ctx, u8 opcode,
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const void *buf, size_t len)
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{
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struct spi_message m;
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struct spi_transfer t[2] = { { .tx_buf = &opcode, .len = 1, },
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{ .tx_buf = buf, .len = len }, };
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spi_message_init(&m);
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spi_message_add_tail(&t[0], &m);
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spi_message_add_tail(&t[1], &m);
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return spi_sync(ctx->spi, &m);
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}
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static void regmap_lock_mutex(void *context)
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{
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struct encx24j600_context *ctx = context;
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mutex_lock(&ctx->mutex);
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}
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static void regmap_unlock_mutex(void *context)
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{
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struct encx24j600_context *ctx = context;
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mutex_unlock(&ctx->mutex);
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}
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static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val,
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size_t len)
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{
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struct encx24j600_context *ctx = context;
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u8 banked_reg = reg & ADDR_MASK;
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u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);
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u8 cmd = RCRU;
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int ret = 0;
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int i = 0;
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u8 tx_buf[2];
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if (reg < 0x80) {
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cmd = RCRCODE | banked_reg;
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if ((banked_reg < 0x16) && (ctx->bank != bank))
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ret = encx24j600_switch_bank(ctx, bank);
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if (unlikely(ret))
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return ret;
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} else {
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/* Translate registers that are more effecient using
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* 3-byte SPI commands
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*/
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switch (reg) {
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case EGPRDPT:
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cmd = RGPRDPT; break;
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case EGPWRPT:
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cmd = RGPWRPT; break;
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case ERXRDPT:
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cmd = RRXRDPT; break;
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case ERXWRPT:
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cmd = RRXWRPT; break;
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case EUDARDPT:
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cmd = RUDARDPT; break;
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case EUDAWRPT:
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cmd = RUDAWRPT; break;
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case EGPDATA:
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case ERXDATA:
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case EUDADATA:
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default:
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return -EINVAL;
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}
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}
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tx_buf[i++] = cmd;
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if (cmd == RCRU)
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tx_buf[i++] = reg;
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ret = spi_write_then_read(ctx->spi, tx_buf, i, val, len);
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return ret;
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}
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static int regmap_encx24j600_sfr_update(struct encx24j600_context *ctx,
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u8 reg, u8 *val, size_t len,
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u8 unbanked_cmd, u8 banked_code)
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{
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u8 banked_reg = reg & ADDR_MASK;
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u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);
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u8 cmd = unbanked_cmd;
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struct spi_message m;
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struct spi_transfer t[3] = { { .tx_buf = &cmd, .len = sizeof(cmd), },
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{ .tx_buf = ®, .len = sizeof(reg), },
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{ .tx_buf = val, .len = len }, };
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if (reg < 0x80) {
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int ret = 0;
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cmd = banked_code | banked_reg;
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if ((banked_reg < 0x16) && (ctx->bank != bank))
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ret = encx24j600_switch_bank(ctx, bank);
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if (unlikely(ret))
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return ret;
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} else {
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/* Translate registers that are more effecient using
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* 3-byte SPI commands
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*/
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switch (reg) {
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case EGPRDPT:
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cmd = WGPRDPT; break;
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case EGPWRPT:
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cmd = WGPWRPT; break;
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case ERXRDPT:
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cmd = WRXRDPT; break;
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case ERXWRPT:
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cmd = WRXWRPT; break;
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case EUDARDPT:
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cmd = WUDARDPT; break;
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case EUDAWRPT:
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cmd = WUDAWRPT; break;
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case EGPDATA:
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case ERXDATA:
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case EUDADATA:
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default:
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return -EINVAL;
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}
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}
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spi_message_init(&m);
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spi_message_add_tail(&t[0], &m);
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if (cmd == unbanked_cmd) {
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t[1].tx_buf = ®
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spi_message_add_tail(&t[1], &m);
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}
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spi_message_add_tail(&t[2], &m);
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return spi_sync(ctx->spi, &m);
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}
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static int regmap_encx24j600_sfr_write(void *context, u8 reg, u8 *val,
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size_t len)
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{
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struct encx24j600_context *ctx = context;
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return regmap_encx24j600_sfr_update(ctx, reg, val, len, WCRU, WCRCODE);
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}
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static int regmap_encx24j600_sfr_set_bits(struct encx24j600_context *ctx,
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u8 reg, u8 val)
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{
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return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFSU, BFSCODE);
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}
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static int regmap_encx24j600_sfr_clr_bits(struct encx24j600_context *ctx,
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u8 reg, u8 val)
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{
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return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFCU, BFCCODE);
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}
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static int regmap_encx24j600_reg_update_bits(void *context, unsigned int reg,
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unsigned int mask,
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unsigned int val)
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{
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struct encx24j600_context *ctx = context;
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int ret = 0;
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unsigned int set_mask = mask & val;
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unsigned int clr_mask = mask & ~val;
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if ((reg >= 0x40 && reg < 0x6c) || reg >= 0x80)
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return -EINVAL;
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if (set_mask & 0xff)
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ret = regmap_encx24j600_sfr_set_bits(ctx, reg, set_mask);
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set_mask = (set_mask & 0xff00) >> 8;
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if ((set_mask & 0xff) && (ret == 0))
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ret = regmap_encx24j600_sfr_set_bits(ctx, reg + 1, set_mask);
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if ((clr_mask & 0xff) && (ret == 0))
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ret = regmap_encx24j600_sfr_clr_bits(ctx, reg, clr_mask);
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clr_mask = (clr_mask & 0xff00) >> 8;
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if ((clr_mask & 0xff) && (ret == 0))
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ret = regmap_encx24j600_sfr_clr_bits(ctx, reg + 1, clr_mask);
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return ret;
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}
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int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data,
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size_t count)
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{
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struct encx24j600_context *ctx = context;
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if (reg < 0xc0)
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return encx24j600_cmdn(ctx, reg, data, count);
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/* SPI 1-byte command. Ignore data */
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return spi_write(ctx->spi, ®, 1);
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}
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EXPORT_SYMBOL_GPL(regmap_encx24j600_spi_write);
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int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count)
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{
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struct encx24j600_context *ctx = context;
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if (reg == RBSEL && count > 1)
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count = 1;
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return spi_write_then_read(ctx->spi, ®, sizeof(reg), data, count);
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}
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EXPORT_SYMBOL_GPL(regmap_encx24j600_spi_read);
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static int regmap_encx24j600_write(void *context, const void *data,
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size_t len)
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{
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u8 *dout = (u8 *)data;
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u8 reg = dout[0];
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++dout;
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--len;
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if (reg > 0xa0)
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return regmap_encx24j600_spi_write(context, reg, dout, len);
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if (len > 2)
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return -EINVAL;
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return regmap_encx24j600_sfr_write(context, reg, dout, len);
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}
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static int regmap_encx24j600_read(void *context,
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const void *reg_buf, size_t reg_size,
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void *val, size_t val_size)
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{
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u8 reg = *(const u8 *)reg_buf;
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if (reg_size != 1) {
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pr_err("%s: reg=%02x reg_size=%zu\n", __func__, reg, reg_size);
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return -EINVAL;
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}
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if (reg > 0xa0)
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return regmap_encx24j600_spi_read(context, reg, val, val_size);
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if (val_size > 2) {
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pr_err("%s: reg=%02x val_size=%zu\n", __func__, reg, val_size);
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return -EINVAL;
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}
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return regmap_encx24j600_sfr_read(context, reg, val, val_size);
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}
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static bool encx24j600_regmap_readable(struct device *dev, unsigned int reg)
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{
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if ((reg < 0x36) ||
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((reg >= 0x40) && (reg < 0x4c)) ||
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((reg >= 0x52) && (reg < 0x56)) ||
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((reg >= 0x60) && (reg < 0x66)) ||
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((reg >= 0x68) && (reg < 0x80)) ||
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((reg >= 0x86) && (reg < 0x92)) ||
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(reg == 0xc8))
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return true;
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else
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return false;
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}
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static bool encx24j600_regmap_writeable(struct device *dev, unsigned int reg)
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{
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if ((reg < 0x12) ||
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((reg >= 0x14) && (reg < 0x1a)) ||
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((reg >= 0x1c) && (reg < 0x36)) ||
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((reg >= 0x40) && (reg < 0x4c)) ||
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((reg >= 0x52) && (reg < 0x56)) ||
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((reg >= 0x60) && (reg < 0x68)) ||
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((reg >= 0x6c) && (reg < 0x80)) ||
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((reg >= 0x86) && (reg < 0x92)) ||
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((reg >= 0xc0) && (reg < 0xc8)) ||
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((reg >= 0xca) && (reg < 0xf0)))
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return true;
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else
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return false;
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}
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static bool encx24j600_regmap_volatile(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case ERXHEAD:
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case EDMACS:
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case ETXSTAT:
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case ETXWIRE:
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case ECON1: /* Can be modified via single byte cmds */
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case ECON2: /* Can be modified via single byte cmds */
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case ESTAT:
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case EIR: /* Can be modified via single byte cmds */
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case MIRD:
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case MISTAT:
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return true;
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default:
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break;
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}
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return false;
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}
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static bool encx24j600_regmap_precious(struct device *dev, unsigned int reg)
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{
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/* single byte cmds are precious */
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if (((reg >= 0xc0) && (reg < 0xc8)) ||
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((reg >= 0xca) && (reg < 0xf0)))
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return true;
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else
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return false;
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}
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static int regmap_encx24j600_phy_reg_read(void *context, unsigned int reg,
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unsigned int *val)
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{
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struct encx24j600_context *ctx = context;
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int ret;
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unsigned int mistat;
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reg = MIREGADR_VAL | (reg & PHREG_MASK);
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ret = regmap_write(ctx->regmap, MIREGADR, reg);
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if (unlikely(ret))
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goto err_out;
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ret = regmap_write(ctx->regmap, MICMD, MIIRD);
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if (unlikely(ret))
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goto err_out;
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usleep_range(26, 100);
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while (((ret = regmap_read(ctx->regmap, MISTAT, &mistat)) == 0) &&
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(mistat & BUSY))
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cpu_relax();
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if (unlikely(ret))
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goto err_out;
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ret = regmap_write(ctx->regmap, MICMD, 0);
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if (unlikely(ret))
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goto err_out;
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ret = regmap_read(ctx->regmap, MIRD, val);
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err_out:
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if (ret)
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pr_err("%s: error %d reading reg %02x\n", __func__, ret,
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reg & PHREG_MASK);
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return ret;
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}
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static int regmap_encx24j600_phy_reg_write(void *context, unsigned int reg,
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unsigned int val)
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{
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struct encx24j600_context *ctx = context;
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int ret;
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unsigned int mistat;
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reg = MIREGADR_VAL | (reg & PHREG_MASK);
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ret = regmap_write(ctx->regmap, MIREGADR, reg);
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if (unlikely(ret))
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goto err_out;
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ret = regmap_write(ctx->regmap, MIWR, val);
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if (unlikely(ret))
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goto err_out;
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usleep_range(26, 100);
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while (((ret = regmap_read(ctx->regmap, MISTAT, &mistat)) == 0) &&
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(mistat & BUSY))
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cpu_relax();
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err_out:
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if (ret)
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pr_err("%s: error %d writing reg %02x=%04x\n", __func__, ret,
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reg & PHREG_MASK, val);
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return ret;
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}
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static bool encx24j600_phymap_readable(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case PHCON1:
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case PHSTAT1:
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case PHANA:
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case PHANLPA:
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case PHANE:
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case PHCON2:
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case PHSTAT2:
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case PHSTAT3:
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return true;
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default:
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return false;
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}
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}
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static bool encx24j600_phymap_writeable(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case PHCON1:
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case PHCON2:
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case PHANA:
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return true;
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case PHSTAT1:
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case PHSTAT2:
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case PHSTAT3:
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case PHANLPA:
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case PHANE:
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default:
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return false;
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}
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}
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static bool encx24j600_phymap_volatile(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case PHSTAT1:
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case PHSTAT2:
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case PHSTAT3:
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case PHANLPA:
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case PHANE:
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case PHCON2:
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return true;
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default:
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return false;
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}
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}
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static struct regmap_config regcfg = {
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.name = "reg",
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.reg_bits = 8,
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.val_bits = 16,
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.max_register = 0xee,
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.reg_stride = 2,
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.cache_type = REGCACHE_RBTREE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.readable_reg = encx24j600_regmap_readable,
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.writeable_reg = encx24j600_regmap_writeable,
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.volatile_reg = encx24j600_regmap_volatile,
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.precious_reg = encx24j600_regmap_precious,
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.lock = regmap_lock_mutex,
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.unlock = regmap_unlock_mutex,
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};
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static struct regmap_bus regmap_encx24j600 = {
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.write = regmap_encx24j600_write,
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.read = regmap_encx24j600_read,
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.reg_update_bits = regmap_encx24j600_reg_update_bits,
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};
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static struct regmap_config phycfg = {
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.name = "phy",
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.reg_bits = 8,
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.val_bits = 16,
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.max_register = 0x1f,
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.cache_type = REGCACHE_RBTREE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.readable_reg = encx24j600_phymap_readable,
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.writeable_reg = encx24j600_phymap_writeable,
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.volatile_reg = encx24j600_phymap_volatile,
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};
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static struct regmap_bus phymap_encx24j600 = {
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.reg_write = regmap_encx24j600_phy_reg_write,
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.reg_read = regmap_encx24j600_phy_reg_read,
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};
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int devm_regmap_init_encx24j600(struct device *dev,
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struct encx24j600_context *ctx)
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{
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mutex_init(&ctx->mutex);
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regcfg.lock_arg = ctx;
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ctx->regmap = devm_regmap_init(dev, ®map_encx24j600, ctx, ®cfg);
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if (IS_ERR(ctx->regmap))
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return PTR_ERR(ctx->regmap);
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ctx->phymap = devm_regmap_init(dev, &phymap_encx24j600, ctx, &phycfg);
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if (IS_ERR(ctx->phymap))
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return PTR_ERR(ctx->phymap);
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return 0;
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}
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EXPORT_SYMBOL_GPL(devm_regmap_init_encx24j600);
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MODULE_LICENSE("GPL");
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