/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* enc28j60_hw.h: EDTP FrameThrower style enc28j60 registers
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*
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* $Id: enc28j60_hw.h,v 1.9 2007/12/14 11:59:16 claudio Exp $
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*/
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#ifndef _ENC28J60_HW_H
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#define _ENC28J60_HW_H
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/*
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* ENC28J60 Control Registers
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* Control register definitions are a combination of address,
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* bank number, and Ethernet/MAC/PHY indicator bits.
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* - Register address (bits 0-4)
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* - Bank number (bits 5-6)
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* - MAC/MII indicator (bit 7)
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*/
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#define ADDR_MASK 0x1F
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#define BANK_MASK 0x60
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#define SPRD_MASK 0x80
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/* All-bank registers */
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#define EIE 0x1B
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#define EIR 0x1C
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#define ESTAT 0x1D
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#define ECON2 0x1E
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#define ECON1 0x1F
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/* Bank 0 registers */
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#define ERDPTL (0x00|0x00)
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#define ERDPTH (0x01|0x00)
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#define EWRPTL (0x02|0x00)
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#define EWRPTH (0x03|0x00)
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#define ETXSTL (0x04|0x00)
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#define ETXSTH (0x05|0x00)
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#define ETXNDL (0x06|0x00)
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#define ETXNDH (0x07|0x00)
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#define ERXSTL (0x08|0x00)
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#define ERXSTH (0x09|0x00)
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#define ERXNDL (0x0A|0x00)
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#define ERXNDH (0x0B|0x00)
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#define ERXRDPTL (0x0C|0x00)
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#define ERXRDPTH (0x0D|0x00)
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#define ERXWRPTL (0x0E|0x00)
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#define ERXWRPTH (0x0F|0x00)
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#define EDMASTL (0x10|0x00)
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#define EDMASTH (0x11|0x00)
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#define EDMANDL (0x12|0x00)
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#define EDMANDH (0x13|0x00)
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#define EDMADSTL (0x14|0x00)
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#define EDMADSTH (0x15|0x00)
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#define EDMACSL (0x16|0x00)
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#define EDMACSH (0x17|0x00)
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/* Bank 1 registers */
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#define EHT0 (0x00|0x20)
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#define EHT1 (0x01|0x20)
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#define EHT2 (0x02|0x20)
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#define EHT3 (0x03|0x20)
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#define EHT4 (0x04|0x20)
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#define EHT5 (0x05|0x20)
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#define EHT6 (0x06|0x20)
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#define EHT7 (0x07|0x20)
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#define EPMM0 (0x08|0x20)
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#define EPMM1 (0x09|0x20)
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#define EPMM2 (0x0A|0x20)
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#define EPMM3 (0x0B|0x20)
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#define EPMM4 (0x0C|0x20)
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#define EPMM5 (0x0D|0x20)
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#define EPMM6 (0x0E|0x20)
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#define EPMM7 (0x0F|0x20)
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#define EPMCSL (0x10|0x20)
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#define EPMCSH (0x11|0x20)
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#define EPMOL (0x14|0x20)
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#define EPMOH (0x15|0x20)
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#define EWOLIE (0x16|0x20)
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#define EWOLIR (0x17|0x20)
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#define ERXFCON (0x18|0x20)
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#define EPKTCNT (0x19|0x20)
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/* Bank 2 registers */
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#define MACON1 (0x00|0x40|SPRD_MASK)
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/* #define MACON2 (0x01|0x40|SPRD_MASK) */
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#define MACON3 (0x02|0x40|SPRD_MASK)
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#define MACON4 (0x03|0x40|SPRD_MASK)
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#define MABBIPG (0x04|0x40|SPRD_MASK)
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#define MAIPGL (0x06|0x40|SPRD_MASK)
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#define MAIPGH (0x07|0x40|SPRD_MASK)
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#define MACLCON1 (0x08|0x40|SPRD_MASK)
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#define MACLCON2 (0x09|0x40|SPRD_MASK)
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#define MAMXFLL (0x0A|0x40|SPRD_MASK)
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#define MAMXFLH (0x0B|0x40|SPRD_MASK)
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#define MAPHSUP (0x0D|0x40|SPRD_MASK)
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#define MICON (0x11|0x40|SPRD_MASK)
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#define MICMD (0x12|0x40|SPRD_MASK)
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#define MIREGADR (0x14|0x40|SPRD_MASK)
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#define MIWRL (0x16|0x40|SPRD_MASK)
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#define MIWRH (0x17|0x40|SPRD_MASK)
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#define MIRDL (0x18|0x40|SPRD_MASK)
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#define MIRDH (0x19|0x40|SPRD_MASK)
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/* Bank 3 registers */
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#define MAADR1 (0x00|0x60|SPRD_MASK)
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#define MAADR0 (0x01|0x60|SPRD_MASK)
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#define MAADR3 (0x02|0x60|SPRD_MASK)
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#define MAADR2 (0x03|0x60|SPRD_MASK)
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#define MAADR5 (0x04|0x60|SPRD_MASK)
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#define MAADR4 (0x05|0x60|SPRD_MASK)
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#define EBSTSD (0x06|0x60)
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#define EBSTCON (0x07|0x60)
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#define EBSTCSL (0x08|0x60)
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#define EBSTCSH (0x09|0x60)
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#define MISTAT (0x0A|0x60|SPRD_MASK)
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#define EREVID (0x12|0x60)
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#define ECOCON (0x15|0x60)
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#define EFLOCON (0x17|0x60)
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#define EPAUSL (0x18|0x60)
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#define EPAUSH (0x19|0x60)
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/* PHY registers */
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#define PHCON1 0x00
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#define PHSTAT1 0x01
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#define PHHID1 0x02
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#define PHHID2 0x03
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#define PHCON2 0x10
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#define PHSTAT2 0x11
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#define PHIE 0x12
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#define PHIR 0x13
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#define PHLCON 0x14
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/* ENC28J60 EIE Register Bit Definitions */
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#define EIE_INTIE 0x80
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#define EIE_PKTIE 0x40
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#define EIE_DMAIE 0x20
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#define EIE_LINKIE 0x10
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#define EIE_TXIE 0x08
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/* #define EIE_WOLIE 0x04 (reserved) */
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#define EIE_TXERIE 0x02
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#define EIE_RXERIE 0x01
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/* ENC28J60 EIR Register Bit Definitions */
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#define EIR_PKTIF 0x40
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#define EIR_DMAIF 0x20
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#define EIR_LINKIF 0x10
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#define EIR_TXIF 0x08
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/* #define EIR_WOLIF 0x04 (reserved) */
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#define EIR_TXERIF 0x02
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#define EIR_RXERIF 0x01
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/* ENC28J60 ESTAT Register Bit Definitions */
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#define ESTAT_INT 0x80
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#define ESTAT_LATECOL 0x10
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#define ESTAT_RXBUSY 0x04
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#define ESTAT_TXABRT 0x02
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#define ESTAT_CLKRDY 0x01
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/* ENC28J60 ECON2 Register Bit Definitions */
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#define ECON2_AUTOINC 0x80
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#define ECON2_PKTDEC 0x40
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#define ECON2_PWRSV 0x20
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#define ECON2_VRPS 0x08
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/* ENC28J60 ECON1 Register Bit Definitions */
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#define ECON1_TXRST 0x80
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#define ECON1_RXRST 0x40
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#define ECON1_DMAST 0x20
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#define ECON1_CSUMEN 0x10
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#define ECON1_TXRTS 0x08
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#define ECON1_RXEN 0x04
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#define ECON1_BSEL1 0x02
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#define ECON1_BSEL0 0x01
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/* ENC28J60 MACON1 Register Bit Definitions */
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#define MACON1_LOOPBK 0x10
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#define MACON1_TXPAUS 0x08
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#define MACON1_RXPAUS 0x04
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#define MACON1_PASSALL 0x02
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#define MACON1_MARXEN 0x01
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/* ENC28J60 MACON2 Register Bit Definitions */
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#define MACON2_MARST 0x80
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#define MACON2_RNDRST 0x40
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#define MACON2_MARXRST 0x08
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#define MACON2_RFUNRST 0x04
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#define MACON2_MATXRST 0x02
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#define MACON2_TFUNRST 0x01
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/* ENC28J60 MACON3 Register Bit Definitions */
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#define MACON3_PADCFG2 0x80
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#define MACON3_PADCFG1 0x40
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#define MACON3_PADCFG0 0x20
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#define MACON3_TXCRCEN 0x10
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#define MACON3_PHDRLEN 0x08
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#define MACON3_HFRMLEN 0x04
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#define MACON3_FRMLNEN 0x02
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#define MACON3_FULDPX 0x01
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/* ENC28J60 MICMD Register Bit Definitions */
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#define MICMD_MIISCAN 0x02
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#define MICMD_MIIRD 0x01
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/* ENC28J60 MISTAT Register Bit Definitions */
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#define MISTAT_NVALID 0x04
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#define MISTAT_SCAN 0x02
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#define MISTAT_BUSY 0x01
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/* ENC28J60 ERXFCON Register Bit Definitions */
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#define ERXFCON_UCEN 0x80
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#define ERXFCON_ANDOR 0x40
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#define ERXFCON_CRCEN 0x20
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#define ERXFCON_PMEN 0x10
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#define ERXFCON_MPEN 0x08
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#define ERXFCON_HTEN 0x04
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#define ERXFCON_MCEN 0x02
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#define ERXFCON_BCEN 0x01
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/* ENC28J60 PHY PHCON1 Register Bit Definitions */
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#define PHCON1_PRST 0x8000
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#define PHCON1_PLOOPBK 0x4000
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#define PHCON1_PPWRSV 0x0800
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#define PHCON1_PDPXMD 0x0100
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/* ENC28J60 PHY PHSTAT1 Register Bit Definitions */
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#define PHSTAT1_PFDPX 0x1000
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#define PHSTAT1_PHDPX 0x0800
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#define PHSTAT1_LLSTAT 0x0004
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#define PHSTAT1_JBSTAT 0x0002
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/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
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#define PHSTAT2_TXSTAT (1 << 13)
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#define PHSTAT2_RXSTAT (1 << 12)
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#define PHSTAT2_COLSTAT (1 << 11)
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#define PHSTAT2_LSTAT (1 << 10)
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#define PHSTAT2_DPXSTAT (1 << 9)
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#define PHSTAT2_PLRITY (1 << 5)
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/* ENC28J60 PHY PHCON2 Register Bit Definitions */
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#define PHCON2_FRCLINK 0x4000
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#define PHCON2_TXDIS 0x2000
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#define PHCON2_JABBER 0x0400
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#define PHCON2_HDLDIS 0x0100
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/* ENC28J60 PHY PHIE Register Bit Definitions */
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#define PHIE_PLNKIE (1 << 4)
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#define PHIE_PGEIE (1 << 1)
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/* ENC28J60 PHY PHIR Register Bit Definitions */
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#define PHIR_PLNKIF (1 << 4)
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#define PHIR_PGEIF (1 << 1)
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/* ENC28J60 Packet Control Byte Bit Definitions */
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#define PKTCTRL_PHUGEEN 0x08
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#define PKTCTRL_PPADEN 0x04
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#define PKTCTRL_PCRCEN 0x02
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#define PKTCTRL_POVERRIDE 0x01
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/* ENC28J60 Transmit Status Vector */
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#define TSV_TXBYTECNT 0
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#define TSV_TXCOLLISIONCNT 16
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#define TSV_TXCRCERROR 20
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#define TSV_TXLENCHKERROR 21
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#define TSV_TXLENOUTOFRANGE 22
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#define TSV_TXDONE 23
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#define TSV_TXMULTICAST 24
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#define TSV_TXBROADCAST 25
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#define TSV_TXPACKETDEFER 26
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#define TSV_TXEXDEFER 27
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#define TSV_TXEXCOLLISION 28
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#define TSV_TXLATECOLLISION 29
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#define TSV_TXGIANT 30
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#define TSV_TXUNDERRUN 31
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#define TSV_TOTBYTETXONWIRE 32
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#define TSV_TXCONTROLFRAME 48
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#define TSV_TXPAUSEFRAME 49
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#define TSV_BACKPRESSUREAPP 50
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#define TSV_TXVLANTAGFRAME 51
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#define TSV_SIZE 7
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#define TSV_BYTEOF(x) ((x) / 8)
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#define TSV_BITMASK(x) (1 << ((x) % 8))
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#define TSV_GETBIT(x, y) (((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0)
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/* ENC28J60 Receive Status Vector */
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#define RSV_RXLONGEVDROPEV 16
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#define RSV_CARRIEREV 18
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#define RSV_CRCERROR 20
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#define RSV_LENCHECKERR 21
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#define RSV_LENOUTOFRANGE 22
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#define RSV_RXOK 23
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#define RSV_RXMULTICAST 24
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#define RSV_RXBROADCAST 25
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#define RSV_DRIBBLENIBBLE 26
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#define RSV_RXCONTROLFRAME 27
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#define RSV_RXPAUSEFRAME 28
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#define RSV_RXUNKNOWNOPCODE 29
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#define RSV_RXTYPEVLAN 30
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#define RSV_SIZE 6
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#define RSV_BITMASK(x) (1 << ((x) - 16))
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#define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0)
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/* SPI operation codes */
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#define ENC28J60_READ_CTRL_REG 0x00
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#define ENC28J60_READ_BUF_MEM 0x3A
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#define ENC28J60_WRITE_CTRL_REG 0x40
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#define ENC28J60_WRITE_BUF_MEM 0x7A
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#define ENC28J60_BIT_FIELD_SET 0x80
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#define ENC28J60_BIT_FIELD_CLR 0xA0
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#define ENC28J60_SOFT_RESET 0xFF
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/* buffer boundaries applied to internal 8K ram
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* entire available packet buffer space is allocated.
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* Give TX buffer space for one full ethernet frame (~1500 bytes)
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* receive buffer gets the rest */
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#define TXSTART_INIT 0x1A00
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#define TXEND_INIT 0x1FFF
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/* Put RX buffer at 0 as suggested by the Errata datasheet */
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#define RXSTART_INIT 0x0000
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#define RXEND_INIT 0x19FF
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/* maximum ethernet frame length */
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#define MAX_FRAMELEN 1518
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/* Preferred half duplex: LEDA: Link status LEDB: Rx/Tx activity */
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#define ENC28J60_LAMPS_MODE 0x3476
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#endif
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