/*
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* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#ifndef _MLX4_EN_H_
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#define _MLX4_EN_H_
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#include <linux/bitops.h>
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#include <linux/compiler.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/netdevice.h>
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#include <linux/if_vlan.h>
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#include <linux/net_tstamp.h>
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#ifdef CONFIG_MLX4_EN_DCB
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#include <linux/dcbnl.h>
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#endif
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#include <linux/cpu_rmap.h>
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#include <linux/ptp_clock_kernel.h>
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#include <net/xdp.h>
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#include <linux/mlx4/device.h>
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#include <linux/mlx4/qp.h>
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#include <linux/mlx4/cq.h>
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#include <linux/mlx4/srq.h>
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#include <linux/mlx4/doorbell.h>
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#include <linux/mlx4/cmd.h>
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#include "en_port.h"
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#include "mlx4_stats.h"
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#define DRV_NAME "mlx4_en"
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#define DRV_VERSION "4.0-0"
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#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
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/*
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* Device constants
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*/
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#define MLX4_EN_PAGE_SHIFT 12
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#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
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#define DEF_RX_RINGS 16
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#define MAX_RX_RINGS 128
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#define MIN_RX_RINGS 1
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#define LOG_TXBB_SIZE 6
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#define TXBB_SIZE BIT(LOG_TXBB_SIZE)
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#define HEADROOM (2048 / TXBB_SIZE + 1)
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#define STAMP_STRIDE 64
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#define STAMP_DWORDS (STAMP_STRIDE / 4)
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#define STAMP_SHIFT 31
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#define STAMP_VAL 0x7fffffff
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#define STATS_DELAY (HZ / 4)
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#define SERVICE_TASK_DELAY (HZ / 4)
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#define MAX_NUM_OF_FS_RULES 256
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#define MLX4_EN_FILTER_HASH_SHIFT 4
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#define MLX4_EN_FILTER_EXPIRY_QUOTA 60
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/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
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#define MAX_DESC_SIZE 512
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#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
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/*
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* OS related constants and tunables
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*/
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#define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
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#define MLX4_EN_PRIV_FLAGS_PHV 2
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#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
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/* Use the maximum between 16384 and a single page */
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#define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
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#define MLX4_EN_MAX_RX_FRAGS 4
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/* Maximum ring sizes */
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#define MLX4_EN_MAX_TX_SIZE 8192
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#define MLX4_EN_MAX_RX_SIZE 8192
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/* Minimum ring size for our page-allocation scheme to work */
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#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
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#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
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#define MLX4_EN_SMALL_PKT_SIZE 64
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#define MLX4_EN_MIN_TX_RING_P_UP 1
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#define MLX4_EN_MAX_TX_RING_P_UP 32
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#define MLX4_EN_NUM_UP_LOW 1
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#define MLX4_EN_NUM_UP_HIGH 8
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#define MLX4_EN_DEF_RX_RING_SIZE 1024
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#define MLX4_EN_DEF_TX_RING_SIZE MLX4_EN_DEF_RX_RING_SIZE
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#define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
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MLX4_EN_NUM_UP_HIGH)
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#define MLX4_EN_DEFAULT_TX_WORK 256
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/* Target number of packets to coalesce with interrupt moderation */
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#define MLX4_EN_RX_COAL_TARGET 44
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#define MLX4_EN_RX_COAL_TIME 0x10
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#define MLX4_EN_TX_COAL_PKTS 16
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#define MLX4_EN_TX_COAL_TIME 0x10
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#define MLX4_EN_MAX_COAL_PKTS U16_MAX
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#define MLX4_EN_MAX_COAL_TIME U16_MAX
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#define MLX4_EN_RX_RATE_LOW 400000
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#define MLX4_EN_RX_COAL_TIME_LOW 0
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#define MLX4_EN_RX_RATE_HIGH 450000
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#define MLX4_EN_RX_COAL_TIME_HIGH 128
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#define MLX4_EN_RX_SIZE_THRESH 1024
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#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
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#define MLX4_EN_SAMPLE_INTERVAL 0
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#define MLX4_EN_AVG_PKT_SMALL 256
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#define MLX4_EN_AUTO_CONF 0xffff
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#define MLX4_EN_DEF_RX_PAUSE 1
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#define MLX4_EN_DEF_TX_PAUSE 1
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/* Interval between successive polls in the Tx routine when polling is used
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instead of interrupts (in per-core Tx rings) - should be power of 2 */
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#define MLX4_EN_TX_POLL_MODER 16
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#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
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#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
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#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
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#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
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#define PREAMBLE_LEN 8
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#define MLX4_SELFTEST_LB_MIN_MTU (MLX4_LOOPBACK_TEST_PAYLOAD + NET_IP_ALIGN + \
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ETH_HLEN + PREAMBLE_LEN)
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/* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
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* headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
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*/
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#define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
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#define ETH_BCAST 0xffffffffffffULL
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#define MLX4_EN_LOOPBACK_RETRIES 5
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#define MLX4_EN_LOOPBACK_TIMEOUT 100
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#ifdef MLX4_EN_PERF_STAT
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/* Number of samples to 'average' */
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#define AVG_SIZE 128
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#define AVG_FACTOR 1024
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#define INC_PERF_COUNTER(cnt) (++(cnt))
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#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
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#define AVG_PERF_COUNTER(cnt, sample) \
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((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
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#define GET_PERF_COUNTER(cnt) (cnt)
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#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
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#else
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#define INC_PERF_COUNTER(cnt) do {} while (0)
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#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
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#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
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#define GET_PERF_COUNTER(cnt) (0)
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#define GET_AVG_PERF_COUNTER(cnt) (0)
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#endif /* MLX4_EN_PERF_STAT */
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/* Constants for TX flow */
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enum {
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MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
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MAX_BF = 256,
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MIN_PKT_LEN = 17,
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};
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/*
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* Configurables
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*/
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enum cq_type {
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/* keep tx types first */
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TX,
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TX_XDP,
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#define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
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RX,
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};
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/*
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* Useful macros
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*/
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#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
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#define XNOR(x, y) (!(x) == !(y))
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struct mlx4_en_tx_info {
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union {
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struct sk_buff *skb;
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struct page *page;
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};
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dma_addr_t map0_dma;
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u32 map0_byte_count;
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u32 nr_txbb;
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u32 nr_bytes;
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u8 linear;
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u8 data_offset;
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u8 inl;
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u8 ts_requested;
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u8 nr_maps;
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} ____cacheline_aligned_in_smp;
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#define MLX4_EN_BIT_DESC_OWN 0x80000000
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#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
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#define MLX4_EN_MEMTYPE_PAD 0x100
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#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
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struct mlx4_en_tx_desc {
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struct mlx4_wqe_ctrl_seg ctrl;
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union {
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struct mlx4_wqe_data_seg data; /* at least one data segment */
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struct mlx4_wqe_lso_seg lso;
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struct mlx4_wqe_inline_seg inl;
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};
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};
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#define MLX4_EN_USE_SRQ 0x01000000
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#define MLX4_EN_CX3_LOW_ID 0x1000
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#define MLX4_EN_CX3_HIGH_ID 0x1005
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struct mlx4_en_rx_alloc {
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struct page *page;
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dma_addr_t dma;
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u32 page_offset;
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};
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#define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
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struct mlx4_en_page_cache {
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u32 index;
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struct {
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struct page *page;
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dma_addr_t dma;
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} buf[MLX4_EN_CACHE_SIZE];
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};
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enum {
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MLX4_EN_TX_RING_STATE_RECOVERING,
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};
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struct mlx4_en_priv;
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struct mlx4_en_tx_ring {
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/* cache line used and dirtied in tx completion
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* (mlx4_en_free_tx_buf())
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*/
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u32 last_nr_txbb;
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u32 cons;
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unsigned long wake_queue;
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struct netdev_queue *tx_queue;
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u32 (*free_tx_desc)(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring,
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int index,
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u64 timestamp, int napi_mode);
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struct mlx4_en_rx_ring *recycle_ring;
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/* cache line used and dirtied in mlx4_en_xmit() */
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u32 prod ____cacheline_aligned_in_smp;
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unsigned int tx_dropped;
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unsigned long bytes;
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unsigned long packets;
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unsigned long tx_csum;
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unsigned long tso_packets;
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unsigned long xmit_more;
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struct mlx4_bf bf;
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/* Following part should be mostly read */
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__be32 doorbell_qpn;
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__be32 mr_key;
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u32 size; /* number of TXBBs */
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u32 size_mask;
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u32 full_size;
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u32 buf_size;
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void *buf;
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struct mlx4_en_tx_info *tx_info;
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int qpn;
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u8 queue_index;
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bool bf_enabled;
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bool bf_alloced;
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u8 hwtstamp_tx_type;
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u8 *bounce_buf;
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/* Not used in fast path
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* Only queue_stopped might be used if BQL is not properly working.
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*/
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unsigned long queue_stopped;
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unsigned long state;
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struct mlx4_hwq_resources sp_wqres;
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struct mlx4_qp sp_qp;
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struct mlx4_qp_context sp_context;
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cpumask_t sp_affinity_mask;
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enum mlx4_qp_state sp_qp_state;
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u16 sp_stride;
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u16 sp_cqn; /* index of port CQ associated with this ring */
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} ____cacheline_aligned_in_smp;
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struct mlx4_en_rx_desc {
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/* actual number of entries depends on rx ring stride */
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struct mlx4_wqe_data_seg data[0];
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};
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struct mlx4_en_rx_ring {
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struct mlx4_hwq_resources wqres;
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u32 size ; /* number of Rx descs*/
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u32 actual_size;
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u32 size_mask;
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u16 stride;
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u16 log_stride;
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u16 cqn; /* index of port CQ associated with this ring */
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u32 prod;
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u32 cons;
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u32 buf_size;
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u8 fcs_del;
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void *buf;
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void *rx_info;
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struct bpf_prog __rcu *xdp_prog;
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struct mlx4_en_page_cache page_cache;
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unsigned long bytes;
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unsigned long packets;
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unsigned long csum_ok;
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unsigned long csum_none;
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unsigned long csum_complete;
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unsigned long rx_alloc_pages;
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unsigned long xdp_drop;
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unsigned long xdp_tx;
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unsigned long xdp_tx_full;
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unsigned long dropped;
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int hwtstamp_rx_filter;
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cpumask_var_t affinity_mask;
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struct xdp_rxq_info xdp_rxq;
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};
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struct mlx4_en_cq {
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struct mlx4_cq mcq;
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struct mlx4_hwq_resources wqres;
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int ring;
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struct net_device *dev;
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union {
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struct napi_struct napi;
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bool xdp_busy;
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};
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int size;
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int buf_size;
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int vector;
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enum cq_type type;
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u16 moder_time;
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u16 moder_cnt;
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struct mlx4_cqe *buf;
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#define MLX4_EN_OPCODE_ERROR 0x1e
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struct irq_desc *irq_desc;
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};
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struct mlx4_en_port_profile {
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u32 flags;
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u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
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u32 rx_ring_num;
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u32 tx_ring_size;
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u32 rx_ring_size;
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u8 num_tx_rings_p_up;
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u8 rx_pause;
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u8 rx_ppp;
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u8 tx_pause;
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u8 tx_ppp;
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u8 num_up;
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int rss_rings;
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int inline_thold;
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struct hwtstamp_config hwtstamp_config;
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};
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struct mlx4_en_profile {
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int udp_rss;
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u8 rss_mask;
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u32 active_ports;
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u32 small_pkt_int;
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u8 no_reset;
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u8 max_num_tx_rings_p_up;
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struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
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};
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struct mlx4_en_dev {
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struct mlx4_dev *dev;
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struct pci_dev *pdev;
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struct mutex state_lock;
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struct net_device *pndev[MLX4_MAX_PORTS + 1];
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struct net_device *upper[MLX4_MAX_PORTS + 1];
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u32 port_cnt;
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bool device_up;
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struct mlx4_en_profile profile;
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u32 LSO_support;
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struct workqueue_struct *workqueue;
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struct device *dma_device;
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void __iomem *uar_map;
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struct mlx4_uar priv_uar;
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struct mlx4_mr mr;
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u32 priv_pdn;
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spinlock_t uar_lock;
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u8 mac_removed[MLX4_MAX_PORTS + 1];
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u32 nominal_c_mult;
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struct cyclecounter cycles;
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seqlock_t clock_lock;
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struct timecounter clock;
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unsigned long last_overflow_check;
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struct ptp_clock *ptp_clock;
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struct ptp_clock_info ptp_clock_info;
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struct notifier_block nb;
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};
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struct mlx4_en_rss_map {
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int base_qpn;
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struct mlx4_qp qps[MAX_RX_RINGS];
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enum mlx4_qp_state state[MAX_RX_RINGS];
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struct mlx4_qp *indir_qp;
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enum mlx4_qp_state indir_state;
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};
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enum mlx4_en_port_flag {
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MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
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MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
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};
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struct mlx4_en_port_state {
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int link_state;
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int link_speed;
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int transceiver;
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u32 flags;
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};
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enum mlx4_en_mclist_act {
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MCLIST_NONE,
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MCLIST_REM,
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MCLIST_ADD,
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};
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struct mlx4_en_mc_list {
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struct list_head list;
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enum mlx4_en_mclist_act action;
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u8 addr[ETH_ALEN];
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u64 reg_id;
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u64 tunnel_reg_id;
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};
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struct mlx4_en_frag_info {
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u16 frag_size;
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u32 frag_stride;
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};
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#ifdef CONFIG_MLX4_EN_DCB
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/* Minimal TC BW - setting to 0 will block traffic */
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#define MLX4_EN_BW_MIN 1
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#define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
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#define MLX4_EN_TC_VENDOR 0
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#define MLX4_EN_TC_ETS 7
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enum dcb_pfc_type {
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pfc_disabled = 0,
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pfc_enabled_full,
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pfc_enabled_tx,
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pfc_enabled_rx
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};
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struct mlx4_en_cee_config {
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bool pfc_state;
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enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH];
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};
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#endif
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struct ethtool_flow_id {
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struct list_head list;
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struct ethtool_rx_flow_spec flow_spec;
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u64 id;
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};
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enum {
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MLX4_EN_FLAG_PROMISC = (1 << 0),
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MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
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/* whether we need to enable hardware loopback by putting dmac
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* in Tx WQE
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*/
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MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
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/* whether we need to drop packets that hardware loopback-ed */
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MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
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MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
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MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),
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#ifdef CONFIG_MLX4_EN_DCB
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MLX4_EN_FLAG_DCB_ENABLED = (1 << 6),
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#endif
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};
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#define PORT_BEACON_MAX_LIMIT (65535)
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#define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
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#define MLX4_EN_MAC_HASH_IDX 5
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struct mlx4_en_stats_bitmap {
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DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
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struct mutex mutex; /* for mutual access to stats bitmap */
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};
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enum {
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MLX4_EN_STATE_FLAG_RESTARTING,
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};
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struct mlx4_en_priv {
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struct mlx4_en_dev *mdev;
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struct mlx4_en_port_profile *prof;
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struct net_device *dev;
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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struct mlx4_en_port_state port_state;
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spinlock_t stats_lock;
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struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
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/* To allow rules removal while port is going down */
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struct list_head ethtool_list;
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unsigned long last_moder_packets[MAX_RX_RINGS];
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unsigned long last_moder_tx_packets;
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unsigned long last_moder_bytes[MAX_RX_RINGS];
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unsigned long last_moder_jiffies;
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int last_moder_time[MAX_RX_RINGS];
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u16 rx_usecs;
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u16 rx_frames;
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u16 tx_usecs;
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u16 tx_frames;
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u32 pkt_rate_low;
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u16 rx_usecs_low;
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u32 pkt_rate_high;
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u16 rx_usecs_high;
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u32 sample_interval;
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u32 adaptive_rx_coal;
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u32 msg_enable;
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u32 loopback_ok;
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u32 validate_loopback;
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struct mlx4_hwq_resources res;
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int link_state;
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int last_link_state;
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bool port_up;
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int port;
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int registered;
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int allocated;
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int stride;
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unsigned char current_mac[ETH_ALEN + 2];
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int mac_index;
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unsigned max_mtu;
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int base_qpn;
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int cqe_factor;
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int cqe_size;
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struct mlx4_en_rss_map rss_map;
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__be32 ctrl_flags;
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u32 flags;
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u8 num_tx_rings_p_up;
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u32 tx_work_limit;
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u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
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u32 rx_ring_num;
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u32 rx_skb_size;
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struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
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u8 num_frags;
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u8 log_rx_info;
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u8 dma_dir;
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u16 rx_headroom;
|
|
struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
|
struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
|
struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
|
struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
|
struct mlx4_qp drop_qp;
|
struct work_struct rx_mode_task;
|
struct work_struct restart_task;
|
struct work_struct linkstate_task;
|
struct delayed_work stats_task;
|
struct delayed_work service_task;
|
struct mlx4_en_perf_stats pstats;
|
struct mlx4_en_pkt_stats pkstats;
|
struct mlx4_en_counter_stats pf_stats;
|
struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
|
struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
|
struct mlx4_en_flow_stats_rx rx_flowstats;
|
struct mlx4_en_flow_stats_tx tx_flowstats;
|
struct mlx4_en_port_stats port_stats;
|
struct mlx4_en_xdp_stats xdp_stats;
|
struct mlx4_en_phy_stats phy_stats;
|
struct mlx4_en_stats_bitmap stats_bitmap;
|
struct list_head mc_list;
|
struct list_head curr_list;
|
u64 broadcast_id;
|
struct mlx4_en_stat_out_mbox hw_stats;
|
int vids[128];
|
bool wol;
|
struct device *ddev;
|
struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
|
struct hwtstamp_config hwtstamp_config;
|
u32 counter_index;
|
|
#ifdef CONFIG_MLX4_EN_DCB
|
#define MLX4_EN_DCB_ENABLED 0x3
|
struct ieee_ets ets;
|
u16 maxrate[IEEE_8021QAZ_MAX_TCS];
|
enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
|
struct mlx4_en_cee_config cee_config;
|
u8 dcbx_cap;
|
#endif
|
#ifdef CONFIG_RFS_ACCEL
|
spinlock_t filters_lock;
|
int last_filter_id;
|
struct list_head filters;
|
struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
|
#endif
|
u64 tunnel_reg_id;
|
__be16 vxlan_port;
|
|
u32 pflags;
|
u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
|
u8 rss_hash_fn;
|
unsigned long state;
|
};
|
|
enum mlx4_en_wol {
|
MLX4_EN_WOL_MAGIC = (1ULL << 61),
|
MLX4_EN_WOL_ENABLED = (1ULL << 62),
|
};
|
|
struct mlx4_mac_entry {
|
struct hlist_node hlist;
|
unsigned char mac[ETH_ALEN + 2];
|
u64 reg_id;
|
struct rcu_head rcu;
|
};
|
|
static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
|
{
|
return buf + idx * cqe_sz;
|
}
|
|
#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
|
|
void mlx4_en_init_ptys2ethtool_map(void);
|
void mlx4_en_update_loopback_state(struct net_device *dev,
|
netdev_features_t features);
|
|
void mlx4_en_destroy_netdev(struct net_device *dev);
|
int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
|
struct mlx4_en_port_profile *prof);
|
|
int mlx4_en_start_port(struct net_device *dev);
|
void mlx4_en_stop_port(struct net_device *dev, int detach);
|
|
void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
|
struct mlx4_en_stats_bitmap *stats_bitmap,
|
u8 rx_ppp, u8 rx_pause,
|
u8 tx_ppp, u8 tx_pause);
|
|
int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
|
struct mlx4_en_priv *tmp,
|
struct mlx4_en_port_profile *prof,
|
bool carry_xdp_prog);
|
void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
|
struct mlx4_en_priv *tmp);
|
|
int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
|
int entries, int ring, enum cq_type mode, int node);
|
void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
|
int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
|
int cq_idx);
|
void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
|
int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
|
void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
|
|
void mlx4_en_tx_irq(struct mlx4_cq *mcq);
|
u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
|
struct net_device *sb_dev);
|
netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
|
netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
|
struct mlx4_en_rx_alloc *frame,
|
struct mlx4_en_priv *priv, unsigned int length,
|
int tx_ind, bool *doorbell_pending);
|
void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
|
bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
|
struct mlx4_en_rx_alloc *frame);
|
|
int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
|
struct mlx4_en_tx_ring **pring,
|
u32 size, u16 stride,
|
int node, int queue_index);
|
void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
|
struct mlx4_en_tx_ring **pring);
|
void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,
|
struct mlx4_en_tx_ring *ring);
|
int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
|
struct mlx4_en_tx_ring *ring,
|
int cq, int user_prio);
|
void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
|
struct mlx4_en_tx_ring *ring);
|
void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
|
void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
|
int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
|
struct mlx4_en_rx_ring **pring,
|
u32 size, u16 stride, int node, int queue_index);
|
void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
|
struct mlx4_en_rx_ring **pring,
|
u32 size, u16 stride);
|
int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
|
void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
|
struct mlx4_en_rx_ring *ring);
|
int mlx4_en_process_rx_cq(struct net_device *dev,
|
struct mlx4_en_cq *cq,
|
int budget);
|
int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
|
int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
|
int mlx4_en_process_tx_cq(struct net_device *dev,
|
struct mlx4_en_cq *cq, int napi_budget);
|
u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
|
struct mlx4_en_tx_ring *ring,
|
int index, u64 timestamp,
|
int napi_mode);
|
u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
|
struct mlx4_en_tx_ring *ring,
|
int index, u64 timestamp,
|
int napi_mode);
|
void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
|
int is_tx, int rss, int qpn, int cqn, int user_prio,
|
struct mlx4_qp_context *context);
|
void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
|
int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
|
int loopback);
|
void mlx4_en_calc_rx_buf(struct net_device *dev);
|
int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
|
void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
|
int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
|
void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
|
int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
|
void mlx4_en_rx_irq(struct mlx4_cq *mcq);
|
|
int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
|
int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
|
|
void mlx4_en_fold_software_stats(struct net_device *dev);
|
int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
|
int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
|
|
#ifdef CONFIG_MLX4_EN_DCB
|
extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
|
extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
|
#endif
|
|
int mlx4_en_setup_tc(struct net_device *dev, u8 up);
|
int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc);
|
|
#ifdef CONFIG_RFS_ACCEL
|
void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
|
#endif
|
|
#define MLX4_EN_NUM_SELF_TEST 5
|
void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
|
void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
|
|
#define DEV_FEATURE_CHANGED(dev, new_features, feature) \
|
((dev->features & feature) ^ (new_features & feature))
|
|
int mlx4_en_moderation_update(struct mlx4_en_priv *priv);
|
int mlx4_en_reset_config(struct net_device *dev,
|
struct hwtstamp_config ts_config,
|
netdev_features_t new_features);
|
void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
|
struct mlx4_en_stats_bitmap *stats_bitmap,
|
u8 rx_ppp, u8 rx_pause,
|
u8 tx_ppp, u8 tx_pause);
|
int mlx4_en_netdev_event(struct notifier_block *this,
|
unsigned long event, void *ptr);
|
|
/*
|
* Functions for time stamping
|
*/
|
u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
|
void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
|
struct skb_shared_hwtstamps *hwts,
|
u64 timestamp);
|
void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
|
void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
|
|
/* Globals
|
*/
|
extern const struct ethtool_ops mlx4_en_ethtool_ops;
|
|
|
|
/*
|
* printk / logging functions
|
*/
|
|
__printf(3, 4)
|
void en_print(const char *level, const struct mlx4_en_priv *priv,
|
const char *format, ...);
|
|
#define en_dbg(mlevel, priv, format, ...) \
|
do { \
|
if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
|
en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
|
} while (0)
|
#define en_warn(priv, format, ...) \
|
en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
|
#define en_err(priv, format, ...) \
|
en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
|
#define en_info(priv, format, ...) \
|
en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
|
|
#define mlx4_err(mdev, format, ...) \
|
pr_err(DRV_NAME " %s: " format, \
|
dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
|
#define mlx4_info(mdev, format, ...) \
|
pr_info(DRV_NAME " %s: " format, \
|
dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
|
#define mlx4_warn(mdev, format, ...) \
|
pr_warn(DRV_NAME " %s: " format, \
|
dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
|
|
#endif
|
