/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* drivers/net/ethernet/ibm/emac/mal.h
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*
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* Memory Access Layer (MAL) support
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*
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* Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
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* <benh@kernel.crashing.org>
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*
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* Based on the arch/ppc version of the driver:
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*
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* Copyright (c) 2004, 2005 Zultys Technologies.
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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*
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* Based on original work by
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* Armin Kuster <akuster@mvista.com>
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* Copyright 2002 MontaVista Softare Inc.
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*/
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#ifndef __IBM_NEWEMAC_MAL_H
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#define __IBM_NEWEMAC_MAL_H
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/*
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* There are some variations on the MAL, we express them in this driver as
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* MAL Version 1 and 2 though that doesn't match any IBM terminology.
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*
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* We call MAL 1 the version in 405GP, 405GPR, 405EP, 440EP, 440GR and
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* NP405H.
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*
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* We call MAL 2 the version in 440GP, 440GX, 440SP, 440SPE and Axon
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*
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* The driver expects a "version" property in the emac node containing
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* a number 1 or 2. New device-trees for EMAC capable platforms are thus
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* required to include that when porting to arch/powerpc.
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*/
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/* MALx DCR registers */
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#define MAL_CFG 0x00
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#define MAL_CFG_SR 0x80000000
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#define MAL_CFG_PLBB 0x00004000
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#define MAL_CFG_OPBBL 0x00000080
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#define MAL_CFG_EOPIE 0x00000004
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#define MAL_CFG_LEA 0x00000002
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#define MAL_CFG_SD 0x00000001
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/* MAL V1 CFG bits */
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#define MAL1_CFG_PLBP_MASK 0x00c00000
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#define MAL1_CFG_PLBP_10 0x00800000
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#define MAL1_CFG_GA 0x00200000
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#define MAL1_CFG_OA 0x00100000
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#define MAL1_CFG_PLBLE 0x00080000
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#define MAL1_CFG_PLBT_MASK 0x00078000
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#define MAL1_CFG_DEFAULT (MAL1_CFG_PLBP_10 | MAL1_CFG_PLBT_MASK)
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/* MAL V2 CFG bits */
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#define MAL2_CFG_RPP_MASK 0x00c00000
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#define MAL2_CFG_RPP_10 0x00800000
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#define MAL2_CFG_RMBS_MASK 0x00300000
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#define MAL2_CFG_WPP_MASK 0x000c0000
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#define MAL2_CFG_WPP_10 0x00080000
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#define MAL2_CFG_WMBS_MASK 0x00030000
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#define MAL2_CFG_PLBLE 0x00008000
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#define MAL2_CFG_DEFAULT (MAL2_CFG_RMBS_MASK | MAL2_CFG_WMBS_MASK | \
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MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10)
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#define MAL_ESR 0x01
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#define MAL_ESR_EVB 0x80000000
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#define MAL_ESR_CIDT 0x40000000
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#define MAL_ESR_CID_MASK 0x3e000000
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#define MAL_ESR_CID_SHIFT 25
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#define MAL_ESR_DE 0x00100000
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#define MAL_ESR_OTE 0x00040000
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#define MAL_ESR_OSE 0x00020000
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#define MAL_ESR_PEIN 0x00010000
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#define MAL_ESR_DEI 0x00000010
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#define MAL_ESR_OTEI 0x00000004
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#define MAL_ESR_OSEI 0x00000002
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#define MAL_ESR_PBEI 0x00000001
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/* MAL V1 ESR bits */
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#define MAL1_ESR_ONE 0x00080000
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#define MAL1_ESR_ONEI 0x00000008
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/* MAL V2 ESR bits */
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#define MAL2_ESR_PTE 0x00800000
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#define MAL2_ESR_PRE 0x00400000
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#define MAL2_ESR_PWE 0x00200000
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#define MAL2_ESR_PTEI 0x00000080
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#define MAL2_ESR_PREI 0x00000040
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#define MAL2_ESR_PWEI 0x00000020
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#define MAL_IER 0x02
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/* MAL IER bits */
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#define MAL_IER_DE 0x00000010
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#define MAL_IER_OTE 0x00000004
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#define MAL_IER_OE 0x00000002
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#define MAL_IER_PE 0x00000001
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/* PLB read/write/timeout errors */
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#define MAL_IER_PTE 0x00000080
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#define MAL_IER_PRE 0x00000040
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#define MAL_IER_PWE 0x00000020
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#define MAL_IER_SOC_EVENTS (MAL_IER_PTE | MAL_IER_PRE | MAL_IER_PWE)
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#define MAL_IER_EVENTS (MAL_IER_SOC_EVENTS | MAL_IER_DE | \
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MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
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#define MAL_TXCASR 0x04
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#define MAL_TXCARR 0x05
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#define MAL_TXEOBISR 0x06
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#define MAL_TXDEIR 0x07
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#define MAL_RXCASR 0x10
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#define MAL_RXCARR 0x11
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#define MAL_RXEOBISR 0x12
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#define MAL_RXDEIR 0x13
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#define MAL_TXCTPR(n) ((n) + 0x20)
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#define MAL_RXCTPR(n) ((n) + 0x40)
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#define MAL_RCBS(n) ((n) + 0x60)
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/* In reality MAL can handle TX buffers up to 4095 bytes long,
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* but this isn't a good round number :) --ebs
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*/
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#define MAL_MAX_TX_SIZE 4080
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#define MAL_MAX_RX_SIZE 4080
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static inline int mal_rx_size(int len)
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{
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len = (len + 0xf) & ~0xf;
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return len > MAL_MAX_RX_SIZE ? MAL_MAX_RX_SIZE : len;
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}
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static inline int mal_tx_chunks(int len)
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{
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return DIV_ROUND_UP(len, MAL_MAX_TX_SIZE);
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}
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#define MAL_CHAN_MASK(n) (0x80000000 >> (n))
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/* MAL Buffer Descriptor structure */
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struct mal_descriptor {
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u16 ctrl; /* MAL / Commac status control bits */
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u16 data_len; /* Max length is 4K-1 (12 bits) */
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u32 data_ptr; /* pointer to actual data buffer */
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};
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/* the following defines are for the MadMAL status and control registers. */
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/* MADMAL transmit and receive status/control bits */
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#define MAL_RX_CTRL_EMPTY 0x8000
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#define MAL_RX_CTRL_WRAP 0x4000
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#define MAL_RX_CTRL_CM 0x2000
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#define MAL_RX_CTRL_LAST 0x1000
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#define MAL_RX_CTRL_FIRST 0x0800
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#define MAL_RX_CTRL_INTR 0x0400
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#define MAL_RX_CTRL_SINGLE (MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST)
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#define MAL_IS_SINGLE_RX(ctrl) (((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE)
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#define MAL_TX_CTRL_READY 0x8000
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#define MAL_TX_CTRL_WRAP 0x4000
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#define MAL_TX_CTRL_CM 0x2000
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#define MAL_TX_CTRL_LAST 0x1000
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#define MAL_TX_CTRL_INTR 0x0400
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struct mal_commac_ops {
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void (*poll_tx) (void *dev);
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int (*poll_rx) (void *dev, int budget);
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int (*peek_rx) (void *dev);
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void (*rxde) (void *dev);
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};
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struct mal_commac {
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struct mal_commac_ops *ops;
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void *dev;
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struct list_head poll_list;
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long flags;
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#define MAL_COMMAC_RX_STOPPED 0
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#define MAL_COMMAC_POLL_DISABLED 1
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u32 tx_chan_mask;
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u32 rx_chan_mask;
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struct list_head list;
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};
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struct mal_instance {
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int version;
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dcr_host_t dcr_host;
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int num_tx_chans; /* Number of TX channels */
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int num_rx_chans; /* Number of RX channels */
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int txeob_irq; /* TX End Of Buffer IRQ */
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int rxeob_irq; /* RX End Of Buffer IRQ */
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int txde_irq; /* TX Descriptor Error IRQ */
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int rxde_irq; /* RX Descriptor Error IRQ */
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int serr_irq; /* MAL System Error IRQ */
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struct list_head poll_list;
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struct napi_struct napi;
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struct list_head list;
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u32 tx_chan_mask;
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u32 rx_chan_mask;
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dma_addr_t bd_dma;
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struct mal_descriptor *bd_virt;
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struct platform_device *ofdev;
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int index;
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spinlock_t lock;
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struct net_device dummy_dev;
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unsigned int features;
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};
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static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg)
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{
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return dcr_read(mal->dcr_host, reg);
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}
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static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val)
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{
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dcr_write(mal->dcr_host, reg, val);
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}
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/* Features of various MAL implementations */
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/* Set if you have interrupt coalescing and you have to clear the SDR
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* register for TXEOB and RXEOB interrupts to work
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*/
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#define MAL_FTR_CLEAR_ICINTSTAT 0x00000001
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/* Set if your MAL has SERR, TXDE, and RXDE OR'd into a single UIC
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* interrupt
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*/
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#define MAL_FTR_COMMON_ERR_INT 0x00000002
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enum {
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MAL_FTRS_ALWAYS = 0,
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MAL_FTRS_POSSIBLE =
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#ifdef CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT
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MAL_FTR_CLEAR_ICINTSTAT |
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#endif
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#ifdef CONFIG_IBM_EMAC_MAL_COMMON_ERR
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MAL_FTR_COMMON_ERR_INT |
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#endif
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0,
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};
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static inline int mal_has_feature(struct mal_instance *dev,
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unsigned long feature)
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{
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return (MAL_FTRS_ALWAYS & feature) ||
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(MAL_FTRS_POSSIBLE & dev->features & feature);
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}
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/* Register MAL devices */
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int mal_init(void);
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void mal_exit(void);
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int mal_register_commac(struct mal_instance *mal,
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struct mal_commac *commac);
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void mal_unregister_commac(struct mal_instance *mal,
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struct mal_commac *commac);
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int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size);
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/* Returns BD ring offset for a particular channel
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(in 'struct mal_descriptor' elements)
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*/
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int mal_tx_bd_offset(struct mal_instance *mal, int channel);
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int mal_rx_bd_offset(struct mal_instance *mal, int channel);
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void mal_enable_tx_channel(struct mal_instance *mal, int channel);
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void mal_disable_tx_channel(struct mal_instance *mal, int channel);
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void mal_enable_rx_channel(struct mal_instance *mal, int channel);
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void mal_disable_rx_channel(struct mal_instance *mal, int channel);
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void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac);
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void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac);
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/* Add/remove EMAC to/from MAL polling list */
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void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac);
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void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac);
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/* Ethtool MAL registers */
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struct mal_regs {
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u32 tx_count;
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u32 rx_count;
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u32 cfg;
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u32 esr;
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u32 ier;
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u32 tx_casr;
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u32 tx_carr;
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u32 tx_eobisr;
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u32 tx_deir;
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u32 rx_casr;
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u32 rx_carr;
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u32 rx_eobisr;
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u32 rx_deir;
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u32 tx_ctpr[32];
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u32 rx_ctpr[32];
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u32 rcbs[32];
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};
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int mal_get_regs_len(struct mal_instance *mal);
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void *mal_dump_regs(struct mal_instance *mal, void *buf);
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#endif /* __IBM_NEWEMAC_MAL_H */
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