/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Huawei HiNIC PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*/
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#ifndef HINIC_HW_EQS_H
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#define HINIC_HW_EQS_H
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#include <linux/types.h>
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#include <linux/workqueue.h>
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#include <linux/pci.h>
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#include <linux/sizes.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include "hinic_hw_if.h"
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#define HINIC_AEQ_CTRL_0_INT_IDX_SHIFT 0
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#define HINIC_AEQ_CTRL_0_DMA_ATTR_SHIFT 12
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#define HINIC_AEQ_CTRL_0_PCI_INTF_IDX_SHIFT 20
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#define HINIC_AEQ_CTRL_0_INT_MODE_SHIFT 31
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#define HINIC_AEQ_CTRL_0_INT_IDX_MASK 0x3FF
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#define HINIC_AEQ_CTRL_0_DMA_ATTR_MASK 0x3F
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#define HINIC_AEQ_CTRL_0_PCI_INTF_IDX_MASK 0x3
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#define HINIC_AEQ_CTRL_0_INT_MODE_MASK 0x1
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#define HINIC_AEQ_CTRL_0_SET(val, member) \
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(((u32)(val) & HINIC_AEQ_CTRL_0_##member##_MASK) << \
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HINIC_AEQ_CTRL_0_##member##_SHIFT)
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#define HINIC_AEQ_CTRL_0_CLEAR(val, member) \
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((val) & (~(HINIC_AEQ_CTRL_0_##member##_MASK \
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<< HINIC_AEQ_CTRL_0_##member##_SHIFT)))
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#define HINIC_AEQ_CTRL_1_LEN_SHIFT 0
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#define HINIC_AEQ_CTRL_1_ELEM_SIZE_SHIFT 24
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#define HINIC_AEQ_CTRL_1_PAGE_SIZE_SHIFT 28
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#define HINIC_AEQ_CTRL_1_LEN_MASK 0x1FFFFF
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#define HINIC_AEQ_CTRL_1_ELEM_SIZE_MASK 0x3
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#define HINIC_AEQ_CTRL_1_PAGE_SIZE_MASK 0xF
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#define HINIC_AEQ_CTRL_1_SET(val, member) \
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(((u32)(val) & HINIC_AEQ_CTRL_1_##member##_MASK) << \
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HINIC_AEQ_CTRL_1_##member##_SHIFT)
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#define HINIC_AEQ_CTRL_1_CLEAR(val, member) \
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((val) & (~(HINIC_AEQ_CTRL_1_##member##_MASK \
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<< HINIC_AEQ_CTRL_1_##member##_SHIFT)))
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#define HINIC_CEQ_CTRL_0_INTR_IDX_SHIFT 0
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#define HINIC_CEQ_CTRL_0_DMA_ATTR_SHIFT 12
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#define HINIC_CEQ_CTRL_0_KICK_THRESH_SHIFT 20
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#define HINIC_CEQ_CTRL_0_PCI_INTF_IDX_SHIFT 24
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#define HINIC_CEQ_CTRL_0_INTR_MODE_SHIFT 31
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#define HINIC_CEQ_CTRL_0_INTR_IDX_MASK 0x3FF
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#define HINIC_CEQ_CTRL_0_DMA_ATTR_MASK 0x3F
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#define HINIC_CEQ_CTRL_0_KICK_THRESH_MASK 0xF
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#define HINIC_CEQ_CTRL_0_PCI_INTF_IDX_MASK 0x3
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#define HINIC_CEQ_CTRL_0_INTR_MODE_MASK 0x1
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#define HINIC_CEQ_CTRL_0_SET(val, member) \
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(((u32)(val) & HINIC_CEQ_CTRL_0_##member##_MASK) << \
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HINIC_CEQ_CTRL_0_##member##_SHIFT)
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#define HINIC_CEQ_CTRL_0_CLEAR(val, member) \
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((val) & (~(HINIC_CEQ_CTRL_0_##member##_MASK \
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<< HINIC_CEQ_CTRL_0_##member##_SHIFT)))
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#define HINIC_CEQ_CTRL_1_LEN_SHIFT 0
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#define HINIC_CEQ_CTRL_1_PAGE_SIZE_SHIFT 28
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#define HINIC_CEQ_CTRL_1_LEN_MASK 0x1FFFFF
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#define HINIC_CEQ_CTRL_1_PAGE_SIZE_MASK 0xF
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#define HINIC_CEQ_CTRL_1_SET(val, member) \
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(((u32)(val) & HINIC_CEQ_CTRL_1_##member##_MASK) << \
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HINIC_CEQ_CTRL_1_##member##_SHIFT)
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#define HINIC_CEQ_CTRL_1_CLEAR(val, member) \
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((val) & (~(HINIC_CEQ_CTRL_1_##member##_MASK \
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<< HINIC_CEQ_CTRL_1_##member##_SHIFT)))
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#define HINIC_EQ_ELEM_DESC_TYPE_SHIFT 0
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#define HINIC_EQ_ELEM_DESC_SRC_SHIFT 7
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#define HINIC_EQ_ELEM_DESC_SIZE_SHIFT 8
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#define HINIC_EQ_ELEM_DESC_WRAPPED_SHIFT 31
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#define HINIC_EQ_ELEM_DESC_TYPE_MASK 0x7F
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#define HINIC_EQ_ELEM_DESC_SRC_MASK 0x1
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#define HINIC_EQ_ELEM_DESC_SIZE_MASK 0xFF
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#define HINIC_EQ_ELEM_DESC_WRAPPED_MASK 0x1
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#define HINIC_EQ_ELEM_DESC_SET(val, member) \
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(((u32)(val) & HINIC_EQ_ELEM_DESC_##member##_MASK) << \
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HINIC_EQ_ELEM_DESC_##member##_SHIFT)
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#define HINIC_EQ_ELEM_DESC_GET(val, member) \
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(((val) >> HINIC_EQ_ELEM_DESC_##member##_SHIFT) & \
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HINIC_EQ_ELEM_DESC_##member##_MASK)
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#define HINIC_EQ_CI_IDX_SHIFT 0
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#define HINIC_EQ_CI_WRAPPED_SHIFT 20
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#define HINIC_EQ_CI_XOR_CHKSUM_SHIFT 24
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#define HINIC_EQ_CI_INT_ARMED_SHIFT 31
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#define HINIC_EQ_CI_IDX_MASK 0xFFFFF
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#define HINIC_EQ_CI_WRAPPED_MASK 0x1
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#define HINIC_EQ_CI_XOR_CHKSUM_MASK 0xF
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#define HINIC_EQ_CI_INT_ARMED_MASK 0x1
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#define HINIC_EQ_CI_SET(val, member) \
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(((u32)(val) & HINIC_EQ_CI_##member##_MASK) << \
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HINIC_EQ_CI_##member##_SHIFT)
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#define HINIC_EQ_CI_CLEAR(val, member) \
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((val) & (~(HINIC_EQ_CI_##member##_MASK \
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<< HINIC_EQ_CI_##member##_SHIFT)))
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#define HINIC_MAX_AEQS 4
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#define HINIC_MAX_CEQS 32
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#define HINIC_AEQE_SIZE 64
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#define HINIC_CEQE_SIZE 4
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#define HINIC_AEQE_DESC_SIZE 4
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#define HINIC_AEQE_DATA_SIZE \
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(HINIC_AEQE_SIZE - HINIC_AEQE_DESC_SIZE)
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#define HINIC_DEFAULT_AEQ_LEN 64
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#define HINIC_DEFAULT_CEQ_LEN 1024
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#define HINIC_EQ_PAGE_SIZE SZ_4K
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#define HINIC_CEQ_ID_CMDQ 0
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enum hinic_eq_type {
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HINIC_AEQ,
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HINIC_CEQ,
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};
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enum hinic_aeq_type {
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HINIC_MBX_FROM_FUNC = 1,
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HINIC_MSG_FROM_MGMT_CPU = 2,
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HINIC_MBX_SEND_RSLT = 5,
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HINIC_MAX_AEQ_EVENTS,
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};
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enum hinic_ceq_type {
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HINIC_CEQ_CMDQ = 3,
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HINIC_MAX_CEQ_EVENTS,
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};
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enum hinic_eqe_state {
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HINIC_EQE_ENABLED = BIT(0),
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HINIC_EQE_RUNNING = BIT(1),
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};
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struct hinic_aeq_elem {
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u8 data[HINIC_AEQE_DATA_SIZE];
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__be32 desc;
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};
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struct hinic_eq_work {
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struct work_struct work;
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void *data;
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};
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struct hinic_eq {
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struct hinic_hwif *hwif;
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struct hinic_hwdev *hwdev;
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enum hinic_eq_type type;
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int q_id;
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u32 q_len;
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u32 page_size;
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u32 cons_idx;
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int wrapped;
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size_t elem_size;
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int num_pages;
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int num_elem_in_pg;
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struct msix_entry msix_entry;
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char irq_name[64];
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dma_addr_t *dma_addr;
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void **virt_addr;
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struct hinic_eq_work aeq_work;
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struct tasklet_struct ceq_tasklet;
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};
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struct hinic_hw_event_cb {
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void (*hwe_handler)(void *handle, void *data, u8 size);
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void *handle;
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unsigned long hwe_state;
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};
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struct hinic_aeqs {
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struct hinic_hwif *hwif;
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struct hinic_eq aeq[HINIC_MAX_AEQS];
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int num_aeqs;
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struct hinic_hw_event_cb hwe_cb[HINIC_MAX_AEQ_EVENTS];
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struct workqueue_struct *workq;
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};
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struct hinic_ceq_cb {
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void (*handler)(void *handle, u32 ceqe_data);
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void *handle;
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enum hinic_eqe_state ceqe_state;
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};
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struct hinic_ceqs {
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struct hinic_hwif *hwif;
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struct hinic_hwdev *hwdev;
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struct hinic_eq ceq[HINIC_MAX_CEQS];
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int num_ceqs;
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struct hinic_ceq_cb ceq_cb[HINIC_MAX_CEQ_EVENTS];
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};
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void hinic_aeq_register_hw_cb(struct hinic_aeqs *aeqs,
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enum hinic_aeq_type event, void *handle,
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void (*hwe_handler)(void *handle, void *data,
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u8 size));
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void hinic_aeq_unregister_hw_cb(struct hinic_aeqs *aeqs,
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enum hinic_aeq_type event);
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void hinic_ceq_register_cb(struct hinic_ceqs *ceqs,
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enum hinic_ceq_type event, void *handle,
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void (*ceq_cb)(void *handle, u32 ceqe_data));
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void hinic_ceq_unregister_cb(struct hinic_ceqs *ceqs,
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enum hinic_ceq_type event);
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int hinic_aeqs_init(struct hinic_aeqs *aeqs, struct hinic_hwif *hwif,
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int num_aeqs, u32 q_len, u32 page_size,
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struct msix_entry *msix_entries);
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void hinic_aeqs_free(struct hinic_aeqs *aeqs);
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int hinic_ceqs_init(struct hinic_ceqs *ceqs, struct hinic_hwif *hwif,
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int num_ceqs, u32 q_len, u32 page_size,
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struct msix_entry *msix_entries);
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void hinic_ceqs_free(struct hinic_ceqs *ceqs);
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void hinic_dump_ceq_info(struct hinic_hwdev *hwdev);
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void hinic_dump_aeq_info(struct hinic_hwdev *hwdev);
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#endif
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