// SPDX-License-Identifier: GPL-2.0-or-later
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/* Copyright (c) 2014 Linaro Ltd.
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* Copyright (c) 2014 Hisilicon Limited.
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*/
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#include <linux/module.h>
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#include <linux/etherdevice.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/ktime.h>
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#include <linux/of_address.h>
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#include <linux/phy.h>
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#include <linux/of_mdio.h>
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#include <linux/of_net.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#define SC_PPE_RESET_DREQ 0x026C
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#define PPE_CFG_RX_ADDR 0x100
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#define PPE_CFG_POOL_GRP 0x300
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#define PPE_CFG_RX_BUF_SIZE 0x400
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#define PPE_CFG_RX_FIFO_SIZE 0x500
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#define PPE_CURR_BUF_CNT 0xa200
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#define GE_DUPLEX_TYPE 0x08
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#define GE_MAX_FRM_SIZE_REG 0x3c
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#define GE_PORT_MODE 0x40
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#define GE_PORT_EN 0x44
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#define GE_SHORT_RUNTS_THR_REG 0x50
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#define GE_TX_LOCAL_PAGE_REG 0x5c
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#define GE_TRANSMIT_CONTROL_REG 0x60
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#define GE_CF_CRC_STRIP_REG 0x1b0
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#define GE_MODE_CHANGE_REG 0x1b4
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#define GE_RECV_CONTROL_REG 0x1e0
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#define GE_STATION_MAC_ADDRESS 0x210
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#define PPE_CFG_BUS_CTRL_REG 0x424
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#define PPE_CFG_RX_CTRL_REG 0x428
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#if defined(CONFIG_HI13X1_GMAC)
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#define PPE_CFG_CPU_ADD_ADDR 0x6D0
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#define PPE_CFG_MAX_FRAME_LEN_REG 0x500
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#define PPE_CFG_RX_PKT_MODE_REG 0x504
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#define PPE_CFG_QOS_VMID_GEN 0x520
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#define PPE_CFG_RX_PKT_INT 0x740
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#define PPE_INTEN 0x700
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#define PPE_INTSTS 0x708
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#define PPE_RINT 0x704
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#define PPE_CFG_STS_MODE 0x880
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#else
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#define PPE_CFG_CPU_ADD_ADDR 0x580
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#define PPE_CFG_MAX_FRAME_LEN_REG 0x408
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#define PPE_CFG_RX_PKT_MODE_REG 0x438
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#define PPE_CFG_QOS_VMID_GEN 0x500
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#define PPE_CFG_RX_PKT_INT 0x538
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#define PPE_INTEN 0x600
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#define PPE_INTSTS 0x608
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#define PPE_RINT 0x604
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#define PPE_CFG_STS_MODE 0x700
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#endif /* CONFIG_HI13X1_GMAC */
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#define PPE_HIS_RX_PKT_CNT 0x804
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#define RESET_DREQ_ALL 0xffffffff
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/* REG_INTERRUPT */
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#define RCV_INT BIT(10)
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#define RCV_NOBUF BIT(8)
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#define RCV_DROP BIT(7)
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#define TX_DROP BIT(6)
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#define DEF_INT_ERR (RCV_NOBUF | RCV_DROP | TX_DROP)
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#define DEF_INT_MASK (RCV_INT | DEF_INT_ERR)
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/* TX descriptor config */
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#define TX_FREE_MEM BIT(0)
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#define TX_READ_ALLOC_L3 BIT(1)
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#if defined(CONFIG_HI13X1_GMAC)
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#define TX_CLEAR_WB BIT(7)
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#define TX_RELEASE_TO_PPE BIT(4)
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#define TX_FINISH_CACHE_INV BIT(6)
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#define TX_POOL_SHIFT 16
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#else
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#define TX_CLEAR_WB BIT(4)
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#define TX_FINISH_CACHE_INV BIT(2)
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#endif
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#define TX_L3_CHECKSUM BIT(5)
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#define TX_LOOP_BACK BIT(11)
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/* RX error */
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#define RX_PKT_DROP BIT(0)
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#define RX_L2_ERR BIT(1)
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#define RX_PKT_ERR (RX_PKT_DROP | RX_L2_ERR)
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#define SGMII_SPEED_1000 0x08
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#define SGMII_SPEED_100 0x07
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#define SGMII_SPEED_10 0x06
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#define MII_SPEED_100 0x01
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#define MII_SPEED_10 0x00
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#define GE_DUPLEX_FULL BIT(0)
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#define GE_DUPLEX_HALF 0x00
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#define GE_MODE_CHANGE_EN BIT(0)
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#define GE_TX_AUTO_NEG BIT(5)
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#define GE_TX_ADD_CRC BIT(6)
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#define GE_TX_SHORT_PAD_THROUGH BIT(7)
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#define GE_RX_STRIP_CRC BIT(0)
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#define GE_RX_STRIP_PAD BIT(3)
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#define GE_RX_PAD_EN BIT(4)
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#define GE_AUTO_NEG_CTL BIT(0)
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#define GE_RX_INT_THRESHOLD BIT(6)
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#define GE_RX_TIMEOUT 0x04
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#define GE_RX_PORT_EN BIT(1)
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#define GE_TX_PORT_EN BIT(2)
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#define PPE_CFG_RX_PKT_ALIGN BIT(18)
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#if defined(CONFIG_HI13X1_GMAC)
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#define PPE_CFG_QOS_VMID_GRP_SHIFT 4
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#define PPE_CFG_RX_CTRL_ALIGN_SHIFT 7
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#define PPE_CFG_STS_RX_PKT_CNT_RC BIT(0)
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#define PPE_CFG_QOS_VMID_MODE BIT(15)
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#define PPE_CFG_BUS_LOCAL_REL (BIT(9) | BIT(15) | BIT(19) | BIT(23))
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/* buf unit size is cache_line_size, which is 64, so the shift is 6 */
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#define PPE_BUF_SIZE_SHIFT 6
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#define PPE_TX_BUF_HOLD BIT(31)
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#define SOC_CACHE_LINE_MASK 0x3F
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#else
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#define PPE_CFG_QOS_VMID_GRP_SHIFT 8
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#define PPE_CFG_RX_CTRL_ALIGN_SHIFT 11
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#define PPE_CFG_STS_RX_PKT_CNT_RC BIT(12)
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#define PPE_CFG_QOS_VMID_MODE BIT(14)
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#define PPE_CFG_BUS_LOCAL_REL BIT(14)
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/* buf unit size is 1, so the shift is 6 */
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#define PPE_BUF_SIZE_SHIFT 0
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#define PPE_TX_BUF_HOLD 0
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#endif /* CONFIG_HI13X1_GMAC */
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#define PPE_CFG_RX_FIFO_FSFU BIT(11)
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#define PPE_CFG_RX_DEPTH_SHIFT 16
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#define PPE_CFG_RX_START_SHIFT 0
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#define PPE_CFG_BUS_BIG_ENDIEN BIT(0)
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#define RX_DESC_NUM 128
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#define TX_DESC_NUM 256
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#define TX_NEXT(N) (((N) + 1) & (TX_DESC_NUM-1))
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#define RX_NEXT(N) (((N) + 1) & (RX_DESC_NUM-1))
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#define GMAC_PPE_RX_PKT_MAX_LEN 379
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#define GMAC_MAX_PKT_LEN 1516
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#define GMAC_MIN_PKT_LEN 31
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#define RX_BUF_SIZE 1600
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#define RESET_TIMEOUT 1000
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#define TX_TIMEOUT (6 * HZ)
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#define DRV_NAME "hip04-ether"
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#define DRV_VERSION "v1.0"
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#define HIP04_MAX_TX_COALESCE_USECS 200
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#define HIP04_MIN_TX_COALESCE_USECS 100
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#define HIP04_MAX_TX_COALESCE_FRAMES 200
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#define HIP04_MIN_TX_COALESCE_FRAMES 100
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struct tx_desc {
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#if defined(CONFIG_HI13X1_GMAC)
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u32 reserved1[2];
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u32 send_addr;
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u16 send_size;
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u16 data_offset;
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u32 reserved2[7];
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u32 cfg;
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u32 wb_addr;
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u32 reserved3[3];
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#else
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u32 send_addr;
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u32 send_size;
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u32 next_addr;
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u32 cfg;
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u32 wb_addr;
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#endif
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} __aligned(64);
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struct rx_desc {
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#if defined(CONFIG_HI13X1_GMAC)
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u32 reserved1[3];
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u16 pkt_len;
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u16 reserved_16;
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u32 reserved2[6];
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u32 pkt_err;
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u32 reserved3[5];
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#else
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u16 reserved_16;
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u16 pkt_len;
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u32 reserve1[3];
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u32 pkt_err;
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u32 reserve2[4];
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#endif
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};
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struct hip04_priv {
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void __iomem *base;
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#if defined(CONFIG_HI13X1_GMAC)
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void __iomem *sysctrl_base;
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#endif
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phy_interface_t phy_mode;
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int chan;
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unsigned int port;
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unsigned int group;
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unsigned int speed;
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unsigned int duplex;
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unsigned int reg_inten;
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struct napi_struct napi;
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struct device *dev;
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struct net_device *ndev;
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struct tx_desc *tx_desc;
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dma_addr_t tx_desc_dma;
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struct sk_buff *tx_skb[TX_DESC_NUM];
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dma_addr_t tx_phys[TX_DESC_NUM];
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unsigned int tx_head;
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int tx_coalesce_frames;
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int tx_coalesce_usecs;
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struct hrtimer tx_coalesce_timer;
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unsigned char *rx_buf[RX_DESC_NUM];
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dma_addr_t rx_phys[RX_DESC_NUM];
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unsigned int rx_head;
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unsigned int rx_buf_size;
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unsigned int rx_cnt_remaining;
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struct device_node *phy_node;
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struct phy_device *phy;
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struct regmap *map;
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struct work_struct tx_timeout_task;
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/* written only by tx cleanup */
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unsigned int tx_tail ____cacheline_aligned_in_smp;
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};
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static inline unsigned int tx_count(unsigned int head, unsigned int tail)
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{
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return (head - tail) % TX_DESC_NUM;
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}
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static void hip04_config_port(struct net_device *ndev, u32 speed, u32 duplex)
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{
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struct hip04_priv *priv = netdev_priv(ndev);
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u32 val;
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priv->speed = speed;
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priv->duplex = duplex;
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switch (priv->phy_mode) {
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case PHY_INTERFACE_MODE_SGMII:
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if (speed == SPEED_1000)
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val = SGMII_SPEED_1000;
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else if (speed == SPEED_100)
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val = SGMII_SPEED_100;
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else
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val = SGMII_SPEED_10;
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break;
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case PHY_INTERFACE_MODE_MII:
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if (speed == SPEED_100)
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val = MII_SPEED_100;
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else
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val = MII_SPEED_10;
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break;
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default:
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netdev_warn(ndev, "not supported mode\n");
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val = MII_SPEED_10;
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break;
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}
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writel_relaxed(val, priv->base + GE_PORT_MODE);
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val = duplex ? GE_DUPLEX_FULL : GE_DUPLEX_HALF;
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writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);
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val = GE_MODE_CHANGE_EN;
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writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG);
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}
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static void hip04_reset_dreq(struct hip04_priv *priv)
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{
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#if defined(CONFIG_HI13X1_GMAC)
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writel_relaxed(RESET_DREQ_ALL, priv->sysctrl_base + SC_PPE_RESET_DREQ);
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#endif
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}
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static void hip04_reset_ppe(struct hip04_priv *priv)
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{
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u32 val, tmp, timeout = 0;
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do {
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regmap_read(priv->map, priv->port * 4 + PPE_CURR_BUF_CNT, &val);
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regmap_read(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, &tmp);
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if (timeout++ > RESET_TIMEOUT)
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break;
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} while (val & 0xfff);
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}
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static void hip04_config_fifo(struct hip04_priv *priv)
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{
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u32 val;
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val = readl_relaxed(priv->base + PPE_CFG_STS_MODE);
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val |= PPE_CFG_STS_RX_PKT_CNT_RC;
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writel_relaxed(val, priv->base + PPE_CFG_STS_MODE);
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val = BIT(priv->group);
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regmap_write(priv->map, priv->port * 4 + PPE_CFG_POOL_GRP, val);
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val = priv->group << PPE_CFG_QOS_VMID_GRP_SHIFT;
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val |= PPE_CFG_QOS_VMID_MODE;
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writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN);
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val = RX_BUF_SIZE >> PPE_BUF_SIZE_SHIFT;
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regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_BUF_SIZE, val);
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val = RX_DESC_NUM << PPE_CFG_RX_DEPTH_SHIFT;
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val |= PPE_CFG_RX_FIFO_FSFU;
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val |= priv->chan << PPE_CFG_RX_START_SHIFT;
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regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_FIFO_SIZE, val);
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val = NET_IP_ALIGN << PPE_CFG_RX_CTRL_ALIGN_SHIFT;
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writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);
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val = PPE_CFG_RX_PKT_ALIGN;
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writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);
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val = PPE_CFG_BUS_LOCAL_REL | PPE_CFG_BUS_BIG_ENDIEN;
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writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);
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val = GMAC_PPE_RX_PKT_MAX_LEN;
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writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
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val = GMAC_MAX_PKT_LEN;
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writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);
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val = GMAC_MIN_PKT_LEN;
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writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);
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val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG);
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val |= GE_TX_AUTO_NEG | GE_TX_ADD_CRC | GE_TX_SHORT_PAD_THROUGH;
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writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);
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val = GE_RX_STRIP_CRC;
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writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);
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val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG);
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val |= GE_RX_STRIP_PAD | GE_RX_PAD_EN;
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writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);
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#ifndef CONFIG_HI13X1_GMAC
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val = GE_AUTO_NEG_CTL;
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writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);
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#endif
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}
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static void hip04_mac_enable(struct net_device *ndev)
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{
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struct hip04_priv *priv = netdev_priv(ndev);
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u32 val;
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/* enable tx & rx */
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val = readl_relaxed(priv->base + GE_PORT_EN);
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val |= GE_RX_PORT_EN | GE_TX_PORT_EN;
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writel_relaxed(val, priv->base + GE_PORT_EN);
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/* clear rx int */
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val = RCV_INT;
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writel_relaxed(val, priv->base + PPE_RINT);
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/* config recv int */
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val = GE_RX_INT_THRESHOLD | GE_RX_TIMEOUT;
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writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT);
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/* enable interrupt */
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priv->reg_inten = DEF_INT_MASK;
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writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
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}
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static void hip04_mac_disable(struct net_device *ndev)
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{
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struct hip04_priv *priv = netdev_priv(ndev);
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u32 val;
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/* disable int */
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priv->reg_inten &= ~(DEF_INT_MASK);
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writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
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/* disable tx & rx */
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val = readl_relaxed(priv->base + GE_PORT_EN);
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val &= ~(GE_RX_PORT_EN | GE_TX_PORT_EN);
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writel_relaxed(val, priv->base + GE_PORT_EN);
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}
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static void hip04_set_xmit_desc(struct hip04_priv *priv, dma_addr_t phys)
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{
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u32 val;
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val = phys >> PPE_BUF_SIZE_SHIFT | PPE_TX_BUF_HOLD;
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writel(val, priv->base + PPE_CFG_CPU_ADD_ADDR);
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}
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static void hip04_set_recv_desc(struct hip04_priv *priv, dma_addr_t phys)
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{
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u32 val;
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val = phys >> PPE_BUF_SIZE_SHIFT;
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regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, val);
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}
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static u32 hip04_recv_cnt(struct hip04_priv *priv)
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{
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return readl(priv->base + PPE_HIS_RX_PKT_CNT);
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}
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static void hip04_update_mac_address(struct net_device *ndev)
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{
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struct hip04_priv *priv = netdev_priv(ndev);
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writel_relaxed(((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])),
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priv->base + GE_STATION_MAC_ADDRESS);
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writel_relaxed(((ndev->dev_addr[2] << 24) | (ndev->dev_addr[3] << 16) |
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(ndev->dev_addr[4] << 8) | (ndev->dev_addr[5])),
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priv->base + GE_STATION_MAC_ADDRESS + 4);
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}
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static int hip04_set_mac_address(struct net_device *ndev, void *addr)
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{
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eth_mac_addr(ndev, addr);
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hip04_update_mac_address(ndev);
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return 0;
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}
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static int hip04_tx_reclaim(struct net_device *ndev, bool force)
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{
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struct hip04_priv *priv = netdev_priv(ndev);
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unsigned tx_tail = priv->tx_tail;
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struct tx_desc *desc;
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unsigned int bytes_compl = 0, pkts_compl = 0;
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unsigned int count;
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smp_rmb();
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count = tx_count(READ_ONCE(priv->tx_head), tx_tail);
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if (count == 0)
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goto out;
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while (count) {
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desc = &priv->tx_desc[tx_tail];
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if (desc->send_addr != 0) {
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if (force)
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desc->send_addr = 0;
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else
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break;
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}
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if (priv->tx_phys[tx_tail]) {
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dma_unmap_single(priv->dev, priv->tx_phys[tx_tail],
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priv->tx_skb[tx_tail]->len,
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DMA_TO_DEVICE);
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priv->tx_phys[tx_tail] = 0;
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}
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pkts_compl++;
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bytes_compl += priv->tx_skb[tx_tail]->len;
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dev_kfree_skb(priv->tx_skb[tx_tail]);
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priv->tx_skb[tx_tail] = NULL;
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tx_tail = TX_NEXT(tx_tail);
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count--;
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}
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priv->tx_tail = tx_tail;
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smp_wmb(); /* Ensure tx_tail visible to xmit */
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out:
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if (pkts_compl || bytes_compl)
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netdev_completed_queue(ndev, pkts_compl, bytes_compl);
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if (unlikely(netif_queue_stopped(ndev)) && (count < (TX_DESC_NUM - 1)))
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netif_wake_queue(ndev);
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return count;
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}
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static void hip04_start_tx_timer(struct hip04_priv *priv)
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{
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unsigned long ns = priv->tx_coalesce_usecs * NSEC_PER_USEC / 2;
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/* allow timer to fire after half the time at the earliest */
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hrtimer_start_range_ns(&priv->tx_coalesce_timer, ns_to_ktime(ns),
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ns, HRTIMER_MODE_REL);
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}
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static netdev_tx_t
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hip04_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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{
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struct hip04_priv *priv = netdev_priv(ndev);
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struct net_device_stats *stats = &ndev->stats;
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unsigned int tx_head = priv->tx_head, count;
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struct tx_desc *desc = &priv->tx_desc[tx_head];
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dma_addr_t phys;
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smp_rmb();
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count = tx_count(tx_head, READ_ONCE(priv->tx_tail));
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if (count == (TX_DESC_NUM - 1)) {
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netif_stop_queue(ndev);
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return NETDEV_TX_BUSY;
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}
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phys = dma_map_single(priv->dev, skb->data, skb->len, DMA_TO_DEVICE);
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if (dma_mapping_error(priv->dev, phys)) {
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dev_kfree_skb(skb);
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return NETDEV_TX_OK;
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}
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priv->tx_skb[tx_head] = skb;
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priv->tx_phys[tx_head] = phys;
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desc->send_size = (__force u32)cpu_to_be32(skb->len);
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#if defined(CONFIG_HI13X1_GMAC)
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desc->cfg = (__force u32)cpu_to_be32(TX_CLEAR_WB | TX_FINISH_CACHE_INV
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| TX_RELEASE_TO_PPE | priv->port << TX_POOL_SHIFT);
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desc->data_offset = (__force u32)cpu_to_be32(phys & SOC_CACHE_LINE_MASK);
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desc->send_addr = (__force u32)cpu_to_be32(phys & ~SOC_CACHE_LINE_MASK);
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#else
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desc->cfg = (__force u32)cpu_to_be32(TX_CLEAR_WB | TX_FINISH_CACHE_INV);
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desc->send_addr = (__force u32)cpu_to_be32(phys);
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#endif
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phys = priv->tx_desc_dma + tx_head * sizeof(struct tx_desc);
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desc->wb_addr = (__force u32)cpu_to_be32(phys +
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offsetof(struct tx_desc, send_addr));
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skb_tx_timestamp(skb);
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hip04_set_xmit_desc(priv, phys);
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count++;
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netdev_sent_queue(ndev, skb->len);
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priv->tx_head = TX_NEXT(tx_head);
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stats->tx_bytes += skb->len;
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stats->tx_packets++;
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/* Ensure tx_head update visible to tx reclaim */
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smp_wmb();
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/* queue is getting full, better start cleaning up now */
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if (count >= priv->tx_coalesce_frames) {
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if (napi_schedule_prep(&priv->napi)) {
|
/* disable rx interrupt and timer */
|
priv->reg_inten &= ~(RCV_INT);
|
writel_relaxed(DEF_INT_MASK & ~RCV_INT,
|
priv->base + PPE_INTEN);
|
hrtimer_cancel(&priv->tx_coalesce_timer);
|
__napi_schedule(&priv->napi);
|
}
|
} else if (!hrtimer_is_queued(&priv->tx_coalesce_timer)) {
|
/* cleanup not pending yet, start a new timer */
|
hip04_start_tx_timer(priv);
|
}
|
|
return NETDEV_TX_OK;
|
}
|
|
static int hip04_rx_poll(struct napi_struct *napi, int budget)
|
{
|
struct hip04_priv *priv = container_of(napi, struct hip04_priv, napi);
|
struct net_device *ndev = priv->ndev;
|
struct net_device_stats *stats = &ndev->stats;
|
struct rx_desc *desc;
|
struct sk_buff *skb;
|
unsigned char *buf;
|
bool last = false;
|
dma_addr_t phys;
|
int rx = 0;
|
int tx_remaining;
|
u16 len;
|
u32 err;
|
|
/* clean up tx descriptors */
|
tx_remaining = hip04_tx_reclaim(ndev, false);
|
priv->rx_cnt_remaining += hip04_recv_cnt(priv);
|
while (priv->rx_cnt_remaining && !last) {
|
buf = priv->rx_buf[priv->rx_head];
|
skb = build_skb(buf, priv->rx_buf_size);
|
if (unlikely(!skb)) {
|
net_dbg_ratelimited("build_skb failed\n");
|
goto refill;
|
}
|
|
dma_unmap_single(priv->dev, priv->rx_phys[priv->rx_head],
|
RX_BUF_SIZE, DMA_FROM_DEVICE);
|
priv->rx_phys[priv->rx_head] = 0;
|
|
desc = (struct rx_desc *)skb->data;
|
len = be16_to_cpu((__force __be16)desc->pkt_len);
|
err = be32_to_cpu((__force __be32)desc->pkt_err);
|
|
if (0 == len) {
|
dev_kfree_skb_any(skb);
|
last = true;
|
} else if ((err & RX_PKT_ERR) || (len >= GMAC_MAX_PKT_LEN)) {
|
dev_kfree_skb_any(skb);
|
stats->rx_dropped++;
|
stats->rx_errors++;
|
} else {
|
skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
|
skb_put(skb, len);
|
skb->protocol = eth_type_trans(skb, ndev);
|
napi_gro_receive(&priv->napi, skb);
|
stats->rx_packets++;
|
stats->rx_bytes += len;
|
rx++;
|
}
|
|
refill:
|
buf = netdev_alloc_frag(priv->rx_buf_size);
|
if (!buf)
|
goto done;
|
phys = dma_map_single(priv->dev, buf,
|
RX_BUF_SIZE, DMA_FROM_DEVICE);
|
if (dma_mapping_error(priv->dev, phys))
|
goto done;
|
priv->rx_buf[priv->rx_head] = buf;
|
priv->rx_phys[priv->rx_head] = phys;
|
hip04_set_recv_desc(priv, phys);
|
|
priv->rx_head = RX_NEXT(priv->rx_head);
|
if (rx >= budget) {
|
--priv->rx_cnt_remaining;
|
goto done;
|
}
|
|
if (--priv->rx_cnt_remaining == 0)
|
priv->rx_cnt_remaining += hip04_recv_cnt(priv);
|
}
|
|
if (!(priv->reg_inten & RCV_INT)) {
|
/* enable rx interrupt */
|
priv->reg_inten |= RCV_INT;
|
writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
|
}
|
napi_complete_done(napi, rx);
|
done:
|
/* start a new timer if necessary */
|
if (rx < budget && tx_remaining)
|
hip04_start_tx_timer(priv);
|
|
return rx;
|
}
|
|
static irqreturn_t hip04_mac_interrupt(int irq, void *dev_id)
|
{
|
struct net_device *ndev = (struct net_device *)dev_id;
|
struct hip04_priv *priv = netdev_priv(ndev);
|
struct net_device_stats *stats = &ndev->stats;
|
u32 ists = readl_relaxed(priv->base + PPE_INTSTS);
|
|
if (!ists)
|
return IRQ_NONE;
|
|
writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT);
|
|
if (unlikely(ists & DEF_INT_ERR)) {
|
if (ists & (RCV_NOBUF | RCV_DROP)) {
|
stats->rx_errors++;
|
stats->rx_dropped++;
|
netdev_err(ndev, "rx drop\n");
|
}
|
if (ists & TX_DROP) {
|
stats->tx_dropped++;
|
netdev_err(ndev, "tx drop\n");
|
}
|
}
|
|
if (ists & RCV_INT && napi_schedule_prep(&priv->napi)) {
|
/* disable rx interrupt */
|
priv->reg_inten &= ~(RCV_INT);
|
writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
|
hrtimer_cancel(&priv->tx_coalesce_timer);
|
__napi_schedule(&priv->napi);
|
}
|
|
return IRQ_HANDLED;
|
}
|
|
static enum hrtimer_restart tx_done(struct hrtimer *hrtimer)
|
{
|
struct hip04_priv *priv;
|
|
priv = container_of(hrtimer, struct hip04_priv, tx_coalesce_timer);
|
|
if (napi_schedule_prep(&priv->napi)) {
|
/* disable rx interrupt */
|
priv->reg_inten &= ~(RCV_INT);
|
writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
|
__napi_schedule(&priv->napi);
|
}
|
|
return HRTIMER_NORESTART;
|
}
|
|
static void hip04_adjust_link(struct net_device *ndev)
|
{
|
struct hip04_priv *priv = netdev_priv(ndev);
|
struct phy_device *phy = priv->phy;
|
|
if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) {
|
hip04_config_port(ndev, phy->speed, phy->duplex);
|
phy_print_status(phy);
|
}
|
}
|
|
static int hip04_mac_open(struct net_device *ndev)
|
{
|
struct hip04_priv *priv = netdev_priv(ndev);
|
int i;
|
|
priv->rx_head = 0;
|
priv->rx_cnt_remaining = 0;
|
priv->tx_head = 0;
|
priv->tx_tail = 0;
|
hip04_reset_ppe(priv);
|
|
for (i = 0; i < RX_DESC_NUM; i++) {
|
dma_addr_t phys;
|
|
phys = dma_map_single(priv->dev, priv->rx_buf[i],
|
RX_BUF_SIZE, DMA_FROM_DEVICE);
|
if (dma_mapping_error(priv->dev, phys))
|
return -EIO;
|
|
priv->rx_phys[i] = phys;
|
hip04_set_recv_desc(priv, phys);
|
}
|
|
if (priv->phy)
|
phy_start(priv->phy);
|
|
netdev_reset_queue(ndev);
|
netif_start_queue(ndev);
|
hip04_mac_enable(ndev);
|
napi_enable(&priv->napi);
|
|
return 0;
|
}
|
|
static int hip04_mac_stop(struct net_device *ndev)
|
{
|
struct hip04_priv *priv = netdev_priv(ndev);
|
int i;
|
|
napi_disable(&priv->napi);
|
netif_stop_queue(ndev);
|
hip04_mac_disable(ndev);
|
hip04_tx_reclaim(ndev, true);
|
hip04_reset_ppe(priv);
|
|
if (priv->phy)
|
phy_stop(priv->phy);
|
|
for (i = 0; i < RX_DESC_NUM; i++) {
|
if (priv->rx_phys[i]) {
|
dma_unmap_single(priv->dev, priv->rx_phys[i],
|
RX_BUF_SIZE, DMA_FROM_DEVICE);
|
priv->rx_phys[i] = 0;
|
}
|
}
|
|
return 0;
|
}
|
|
static void hip04_timeout(struct net_device *ndev, unsigned int txqueue)
|
{
|
struct hip04_priv *priv = netdev_priv(ndev);
|
|
schedule_work(&priv->tx_timeout_task);
|
}
|
|
static void hip04_tx_timeout_task(struct work_struct *work)
|
{
|
struct hip04_priv *priv;
|
|
priv = container_of(work, struct hip04_priv, tx_timeout_task);
|
hip04_mac_stop(priv->ndev);
|
hip04_mac_open(priv->ndev);
|
}
|
|
static int hip04_get_coalesce(struct net_device *netdev,
|
struct ethtool_coalesce *ec)
|
{
|
struct hip04_priv *priv = netdev_priv(netdev);
|
|
ec->tx_coalesce_usecs = priv->tx_coalesce_usecs;
|
ec->tx_max_coalesced_frames = priv->tx_coalesce_frames;
|
|
return 0;
|
}
|
|
static int hip04_set_coalesce(struct net_device *netdev,
|
struct ethtool_coalesce *ec)
|
{
|
struct hip04_priv *priv = netdev_priv(netdev);
|
|
if ((ec->tx_coalesce_usecs > HIP04_MAX_TX_COALESCE_USECS ||
|
ec->tx_coalesce_usecs < HIP04_MIN_TX_COALESCE_USECS) ||
|
(ec->tx_max_coalesced_frames > HIP04_MAX_TX_COALESCE_FRAMES ||
|
ec->tx_max_coalesced_frames < HIP04_MIN_TX_COALESCE_FRAMES))
|
return -EINVAL;
|
|
priv->tx_coalesce_usecs = ec->tx_coalesce_usecs;
|
priv->tx_coalesce_frames = ec->tx_max_coalesced_frames;
|
|
return 0;
|
}
|
|
static void hip04_get_drvinfo(struct net_device *netdev,
|
struct ethtool_drvinfo *drvinfo)
|
{
|
strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
|
strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
|
}
|
|
static const struct ethtool_ops hip04_ethtool_ops = {
|
.supported_coalesce_params = ETHTOOL_COALESCE_TX_USECS |
|
ETHTOOL_COALESCE_TX_MAX_FRAMES,
|
.get_coalesce = hip04_get_coalesce,
|
.set_coalesce = hip04_set_coalesce,
|
.get_drvinfo = hip04_get_drvinfo,
|
};
|
|
static const struct net_device_ops hip04_netdev_ops = {
|
.ndo_open = hip04_mac_open,
|
.ndo_stop = hip04_mac_stop,
|
.ndo_start_xmit = hip04_mac_start_xmit,
|
.ndo_set_mac_address = hip04_set_mac_address,
|
.ndo_tx_timeout = hip04_timeout,
|
.ndo_validate_addr = eth_validate_addr,
|
};
|
|
static int hip04_alloc_ring(struct net_device *ndev, struct device *d)
|
{
|
struct hip04_priv *priv = netdev_priv(ndev);
|
int i;
|
|
priv->tx_desc = dma_alloc_coherent(d,
|
TX_DESC_NUM * sizeof(struct tx_desc),
|
&priv->tx_desc_dma, GFP_KERNEL);
|
if (!priv->tx_desc)
|
return -ENOMEM;
|
|
priv->rx_buf_size = RX_BUF_SIZE +
|
SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
|
for (i = 0; i < RX_DESC_NUM; i++) {
|
priv->rx_buf[i] = netdev_alloc_frag(priv->rx_buf_size);
|
if (!priv->rx_buf[i])
|
return -ENOMEM;
|
}
|
|
return 0;
|
}
|
|
static void hip04_free_ring(struct net_device *ndev, struct device *d)
|
{
|
struct hip04_priv *priv = netdev_priv(ndev);
|
int i;
|
|
for (i = 0; i < RX_DESC_NUM; i++)
|
if (priv->rx_buf[i])
|
skb_free_frag(priv->rx_buf[i]);
|
|
for (i = 0; i < TX_DESC_NUM; i++)
|
if (priv->tx_skb[i])
|
dev_kfree_skb_any(priv->tx_skb[i]);
|
|
dma_free_coherent(d, TX_DESC_NUM * sizeof(struct tx_desc),
|
priv->tx_desc, priv->tx_desc_dma);
|
}
|
|
static int hip04_mac_probe(struct platform_device *pdev)
|
{
|
struct device *d = &pdev->dev;
|
struct device_node *node = d->of_node;
|
struct of_phandle_args arg;
|
struct net_device *ndev;
|
struct hip04_priv *priv;
|
int irq;
|
int ret;
|
|
ndev = alloc_etherdev(sizeof(struct hip04_priv));
|
if (!ndev)
|
return -ENOMEM;
|
|
priv = netdev_priv(ndev);
|
priv->dev = d;
|
priv->ndev = ndev;
|
platform_set_drvdata(pdev, ndev);
|
SET_NETDEV_DEV(ndev, &pdev->dev);
|
|
priv->base = devm_platform_ioremap_resource(pdev, 0);
|
if (IS_ERR(priv->base)) {
|
ret = PTR_ERR(priv->base);
|
goto init_fail;
|
}
|
|
#if defined(CONFIG_HI13X1_GMAC)
|
priv->sysctrl_base = devm_platform_ioremap_resource(pdev, 1);
|
if (IS_ERR(priv->sysctrl_base)) {
|
ret = PTR_ERR(priv->sysctrl_base);
|
goto init_fail;
|
}
|
#endif
|
|
ret = of_parse_phandle_with_fixed_args(node, "port-handle", 3, 0, &arg);
|
if (ret < 0) {
|
dev_warn(d, "no port-handle\n");
|
goto init_fail;
|
}
|
|
priv->port = arg.args[0];
|
priv->chan = arg.args[1] * RX_DESC_NUM;
|
priv->group = arg.args[2];
|
|
hrtimer_init(&priv->tx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
|
|
/* BQL will try to keep the TX queue as short as possible, but it can't
|
* be faster than tx_coalesce_usecs, so we need a fast timeout here,
|
* but also long enough to gather up enough frames to ensure we don't
|
* get more interrupts than necessary.
|
* 200us is enough for 16 frames of 1500 bytes at gigabit ethernet rate
|
*/
|
priv->tx_coalesce_frames = TX_DESC_NUM * 3 / 4;
|
priv->tx_coalesce_usecs = 200;
|
priv->tx_coalesce_timer.function = tx_done;
|
|
priv->map = syscon_node_to_regmap(arg.np);
|
if (IS_ERR(priv->map)) {
|
dev_warn(d, "no syscon hisilicon,hip04-ppe\n");
|
ret = PTR_ERR(priv->map);
|
goto init_fail;
|
}
|
|
ret = of_get_phy_mode(node, &priv->phy_mode);
|
if (ret) {
|
dev_warn(d, "not find phy-mode\n");
|
goto init_fail;
|
}
|
|
irq = platform_get_irq(pdev, 0);
|
if (irq <= 0) {
|
ret = -EINVAL;
|
goto init_fail;
|
}
|
|
ret = devm_request_irq(d, irq, hip04_mac_interrupt,
|
0, pdev->name, ndev);
|
if (ret) {
|
netdev_err(ndev, "devm_request_irq failed\n");
|
goto init_fail;
|
}
|
|
priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
|
if (priv->phy_node) {
|
priv->phy = of_phy_connect(ndev, priv->phy_node,
|
&hip04_adjust_link,
|
0, priv->phy_mode);
|
if (!priv->phy) {
|
ret = -EPROBE_DEFER;
|
goto init_fail;
|
}
|
}
|
|
INIT_WORK(&priv->tx_timeout_task, hip04_tx_timeout_task);
|
|
ndev->netdev_ops = &hip04_netdev_ops;
|
ndev->ethtool_ops = &hip04_ethtool_ops;
|
ndev->watchdog_timeo = TX_TIMEOUT;
|
ndev->priv_flags |= IFF_UNICAST_FLT;
|
ndev->irq = irq;
|
netif_napi_add(ndev, &priv->napi, hip04_rx_poll, NAPI_POLL_WEIGHT);
|
|
hip04_reset_dreq(priv);
|
hip04_reset_ppe(priv);
|
if (priv->phy_mode == PHY_INTERFACE_MODE_MII)
|
hip04_config_port(ndev, SPEED_100, DUPLEX_FULL);
|
|
hip04_config_fifo(priv);
|
eth_random_addr(ndev->dev_addr);
|
hip04_update_mac_address(ndev);
|
|
ret = hip04_alloc_ring(ndev, d);
|
if (ret) {
|
netdev_err(ndev, "alloc ring fail\n");
|
goto alloc_fail;
|
}
|
|
ret = register_netdev(ndev);
|
if (ret)
|
goto alloc_fail;
|
|
return 0;
|
|
alloc_fail:
|
hip04_free_ring(ndev, d);
|
init_fail:
|
of_node_put(priv->phy_node);
|
free_netdev(ndev);
|
return ret;
|
}
|
|
static int hip04_remove(struct platform_device *pdev)
|
{
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
struct hip04_priv *priv = netdev_priv(ndev);
|
struct device *d = &pdev->dev;
|
|
if (priv->phy)
|
phy_disconnect(priv->phy);
|
|
hip04_free_ring(ndev, d);
|
unregister_netdev(ndev);
|
of_node_put(priv->phy_node);
|
cancel_work_sync(&priv->tx_timeout_task);
|
free_netdev(ndev);
|
|
return 0;
|
}
|
|
static const struct of_device_id hip04_mac_match[] = {
|
{ .compatible = "hisilicon,hip04-mac" },
|
{ }
|
};
|
|
MODULE_DEVICE_TABLE(of, hip04_mac_match);
|
|
static struct platform_driver hip04_mac_driver = {
|
.probe = hip04_mac_probe,
|
.remove = hip04_remove,
|
.driver = {
|
.name = DRV_NAME,
|
.of_match_table = hip04_mac_match,
|
},
|
};
|
module_platform_driver(hip04_mac_driver);
|
|
MODULE_DESCRIPTION("HISILICON P04 Ethernet driver");
|
MODULE_LICENSE("GPL");
|
