/*
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* libcxgb_ppm.h: Chelsio common library for T3/T4/T5 iSCSI ddp operation
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*
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* Copyright (c) 2016 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Written by: Karen Xie (kxie@chelsio.com)
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*/
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#ifndef __LIBCXGB_PPM_H__
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#define __LIBCXGB_PPM_H__
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <linux/debugfs.h>
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#include <linux/list.h>
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#include <linux/netdevice.h>
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#include <linux/scatterlist.h>
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#include <linux/skbuff.h>
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#include <linux/vmalloc.h>
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#include <linux/bitmap.h>
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struct cxgbi_pagepod_hdr {
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u32 vld_tid;
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u32 pgsz_tag_clr;
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u32 max_offset;
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u32 page_offset;
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u64 rsvd;
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};
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#define PPOD_PAGES_MAX 4
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struct cxgbi_pagepod {
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struct cxgbi_pagepod_hdr hdr;
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__be64 addr[PPOD_PAGES_MAX + 1];
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};
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/* ddp tag format
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* for a 32-bit tag:
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* bit #
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* 31 ..... ..... 0
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* X Y...Y Z...Z, where
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* ^ ^^^^^ ^^^^
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* | | |____ when ddp bit = 0: color bits
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* | |
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* | |____ when ddp bit = 0: idx into the ddp memory region
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* |
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* |____ ddp bit: 0 - ddp tag, 1 - non-ddp tag
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*
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* [page selector:2] [sw/free bits] [0] [idx] [color:6]
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*/
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#define DDP_PGIDX_MAX 4
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#define DDP_PGSZ_BASE_SHIFT 12 /* base page 4K */
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struct cxgbi_task_tag_info {
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unsigned char flags;
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#define CXGBI_PPOD_INFO_FLAG_VALID 0x1
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#define CXGBI_PPOD_INFO_FLAG_MAPPED 0x2
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unsigned char cid;
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unsigned short pg_shift;
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unsigned int npods;
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unsigned int idx;
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unsigned int tag;
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struct cxgbi_pagepod_hdr hdr;
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int nents;
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int nr_pages;
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struct scatterlist *sgl;
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};
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struct cxgbi_tag_format {
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unsigned char pgsz_order[DDP_PGIDX_MAX];
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unsigned char pgsz_idx_dflt;
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unsigned char free_bits:4;
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unsigned char color_bits:4;
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unsigned char idx_bits;
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unsigned char rsvd_bits;
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unsigned int no_ddp_mask;
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unsigned int idx_mask;
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unsigned int color_mask;
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unsigned int idx_clr_mask;
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unsigned int rsvd_mask;
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};
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struct cxgbi_ppod_data {
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unsigned char pg_idx:2;
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unsigned char color:6;
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unsigned char chan_id;
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unsigned short npods;
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unsigned long caller_data;
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};
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/* per cpu ppm pool */
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struct cxgbi_ppm_pool {
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unsigned int base; /* base index */
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unsigned int next; /* next possible free index */
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spinlock_t lock; /* ppm pool lock */
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unsigned long bmap[];
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} ____cacheline_aligned_in_smp;
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struct cxgbi_ppm {
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struct kref refcnt;
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struct net_device *ndev; /* net_device, 1st port */
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struct pci_dev *pdev;
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void *lldev;
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void **ppm_pp;
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struct cxgbi_tag_format tformat;
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unsigned int ppmax;
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unsigned int llimit;
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unsigned int base_idx;
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unsigned int pool_rsvd;
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unsigned int pool_index_max;
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struct cxgbi_ppm_pool __percpu *pool;
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/* map lock */
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spinlock_t map_lock; /* ppm map lock */
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unsigned int bmap_index_max;
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unsigned int next;
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unsigned int max_index_in_edram;
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unsigned long *ppod_bmap;
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struct cxgbi_ppod_data ppod_data[];
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};
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#define DDP_THRESHOLD 512
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#define PPOD_PAGES_SHIFT 2 /* 4 pages per pod */
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#define IPPOD_SIZE sizeof(struct cxgbi_pagepod) /* 64 */
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#define PPOD_SIZE_SHIFT 6
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/* page pods are allocated in groups of this size (must be power of 2) */
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#define PPOD_CLUSTER_SIZE 16U
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#define ULPMEM_DSGL_MAX_NPPODS 16 /* 1024/PPOD_SIZE */
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#define ULPMEM_IDATA_MAX_NPPODS 3 /* (PPOD_SIZE * 3 + ulptx hdr) < 256B */
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#define PCIE_MEMWIN_MAX_NPPODS 16 /* 1024/PPOD_SIZE */
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#define PPOD_COLOR_SHIFT 0
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#define PPOD_COLOR(x) ((x) << PPOD_COLOR_SHIFT)
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#define PPOD_IDX_SHIFT 6
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#define PPOD_IDX_MAX_SIZE 24
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#define PPOD_TID_SHIFT 0
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#define PPOD_TID(x) ((x) << PPOD_TID_SHIFT)
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#define PPOD_TAG_SHIFT 6
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#define PPOD_TAG(x) ((x) << PPOD_TAG_SHIFT)
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#define PPOD_VALID_SHIFT 24
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#define PPOD_VALID(x) ((x) << PPOD_VALID_SHIFT)
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#define PPOD_VALID_FLAG PPOD_VALID(1U)
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#define PPOD_PI_EXTRACT_CTL_SHIFT 31
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#define PPOD_PI_EXTRACT_CTL(x) ((x) << PPOD_PI_EXTRACT_CTL_SHIFT)
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#define PPOD_PI_EXTRACT_CTL_FLAG V_PPOD_PI_EXTRACT_CTL(1U)
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#define PPOD_PI_TYPE_SHIFT 29
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#define PPOD_PI_TYPE_MASK 0x3
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#define PPOD_PI_TYPE(x) ((x) << PPOD_PI_TYPE_SHIFT)
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#define PPOD_PI_CHECK_CTL_SHIFT 27
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#define PPOD_PI_CHECK_CTL_MASK 0x3
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#define PPOD_PI_CHECK_CTL(x) ((x) << PPOD_PI_CHECK_CTL_SHIFT)
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#define PPOD_PI_REPORT_CTL_SHIFT 25
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#define PPOD_PI_REPORT_CTL_MASK 0x3
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#define PPOD_PI_REPORT_CTL(x) ((x) << PPOD_PI_REPORT_CTL_SHIFT)
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static inline int cxgbi_ppm_is_ddp_tag(struct cxgbi_ppm *ppm, u32 tag)
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{
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return !(tag & ppm->tformat.no_ddp_mask);
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}
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static inline int cxgbi_ppm_sw_tag_is_usable(struct cxgbi_ppm *ppm,
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u32 tag)
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{
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/* the sw tag must be using <= 31 bits */
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return !(tag & 0x80000000U);
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}
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static inline int cxgbi_ppm_make_non_ddp_tag(struct cxgbi_ppm *ppm,
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u32 sw_tag,
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u32 *final_tag)
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{
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struct cxgbi_tag_format *tformat = &ppm->tformat;
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if (!cxgbi_ppm_sw_tag_is_usable(ppm, sw_tag)) {
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pr_info("sw_tag 0x%x NOT usable.\n", sw_tag);
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return -EINVAL;
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}
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if (!sw_tag) {
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*final_tag = tformat->no_ddp_mask;
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} else {
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unsigned int shift = tformat->idx_bits + tformat->color_bits;
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u32 lower = sw_tag & tformat->idx_clr_mask;
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u32 upper = (sw_tag >> shift) << (shift + 1);
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*final_tag = upper | tformat->no_ddp_mask | lower;
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}
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return 0;
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}
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static inline u32 cxgbi_ppm_decode_non_ddp_tag(struct cxgbi_ppm *ppm,
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u32 tag)
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{
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struct cxgbi_tag_format *tformat = &ppm->tformat;
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unsigned int shift = tformat->idx_bits + tformat->color_bits;
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u32 lower = tag & tformat->idx_clr_mask;
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u32 upper = (tag >> tformat->rsvd_bits) << shift;
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return upper | lower;
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}
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static inline u32 cxgbi_ppm_ddp_tag_get_idx(struct cxgbi_ppm *ppm,
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u32 ddp_tag)
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{
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u32 hw_idx = (ddp_tag >> PPOD_IDX_SHIFT) &
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ppm->tformat.idx_mask;
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return hw_idx - ppm->base_idx;
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}
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static inline u32 cxgbi_ppm_make_ddp_tag(unsigned int hw_idx,
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unsigned char color)
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{
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return (hw_idx << PPOD_IDX_SHIFT) | ((u32)color);
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}
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static inline unsigned long
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cxgbi_ppm_get_tag_caller_data(struct cxgbi_ppm *ppm,
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u32 ddp_tag)
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{
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u32 idx = cxgbi_ppm_ddp_tag_get_idx(ppm, ddp_tag);
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return ppm->ppod_data[idx].caller_data;
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}
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/* sw bits are the free bits */
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static inline int cxgbi_ppm_ddp_tag_update_sw_bits(struct cxgbi_ppm *ppm,
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u32 val, u32 orig_tag,
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u32 *final_tag)
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{
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struct cxgbi_tag_format *tformat = &ppm->tformat;
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u32 v = val >> tformat->free_bits;
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if (v) {
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pr_info("sw_bits 0x%x too large, avail bits %u.\n",
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val, tformat->free_bits);
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return -EINVAL;
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}
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if (!cxgbi_ppm_is_ddp_tag(ppm, orig_tag))
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return -EINVAL;
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*final_tag = (val << tformat->rsvd_bits) |
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(orig_tag & ppm->tformat.rsvd_mask);
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return 0;
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}
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static inline void cxgbi_ppm_ppod_clear(struct cxgbi_pagepod *ppod)
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{
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ppod->hdr.vld_tid = 0U;
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}
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static inline void cxgbi_tagmask_check(unsigned int tagmask,
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struct cxgbi_tag_format *tformat)
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{
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unsigned int bits = fls(tagmask);
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/* reserve top most 2 bits for page selector */
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tformat->free_bits = 32 - 2 - bits;
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tformat->rsvd_bits = bits;
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tformat->color_bits = PPOD_IDX_SHIFT;
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tformat->idx_bits = bits - 1 - PPOD_IDX_SHIFT;
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tformat->no_ddp_mask = 1 << (bits - 1);
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tformat->idx_mask = (1 << tformat->idx_bits) - 1;
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tformat->color_mask = (1 << PPOD_IDX_SHIFT) - 1;
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tformat->idx_clr_mask = (1 << (bits - 1)) - 1;
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tformat->rsvd_mask = (1 << bits) - 1;
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pr_info("ippm: tagmask 0x%x, rsvd %u=%u+%u+1, mask 0x%x,0x%x, "
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"pg %u,%u,%u,%u.\n",
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tagmask, tformat->rsvd_bits, tformat->idx_bits,
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tformat->color_bits, tformat->no_ddp_mask, tformat->rsvd_mask,
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tformat->pgsz_order[0], tformat->pgsz_order[1],
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tformat->pgsz_order[2], tformat->pgsz_order[3]);
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}
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int cxgbi_ppm_find_page_index(struct cxgbi_ppm *ppm, unsigned long pgsz);
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void cxgbi_ppm_make_ppod_hdr(struct cxgbi_ppm *ppm, u32 tag,
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unsigned int tid, unsigned int offset,
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unsigned int length,
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struct cxgbi_pagepod_hdr *hdr);
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void cxgbi_ppm_ppod_release(struct cxgbi_ppm *, u32 idx);
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int cxgbi_ppm_ppods_reserve(struct cxgbi_ppm *, unsigned short nr_pages,
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u32 per_tag_pg_idx, u32 *ppod_idx, u32 *ddp_tag,
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unsigned long caller_data);
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int cxgbi_ppm_init(void **ppm_pp, struct net_device *, struct pci_dev *,
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void *lldev, struct cxgbi_tag_format *,
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unsigned int iscsi_size, unsigned int llimit,
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unsigned int start, unsigned int reserve_factor,
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unsigned int edram_start, unsigned int edram_size);
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int cxgbi_ppm_release(struct cxgbi_ppm *ppm);
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void cxgbi_tagmask_check(unsigned int tagmask, struct cxgbi_tag_format *);
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unsigned int cxgbi_tagmask_set(unsigned int ppmax);
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#endif /*__LIBCXGB_PPM_H__*/
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