/* SPDX-License-Identifier: GPL-2.0 */
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/* $Date: 2005/03/07 23:59:05 $ $RCSfile: fpga_defs.h,v $ $Revision: 1.4 $ */
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/*
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* FPGA specific definitions
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*/
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#ifndef __CHELSIO_FPGA_DEFS_H__
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#define __CHELSIO_FPGA_DEFS_H__
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#define FPGA_PCIX_ADDR_VERSION 0xA08
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#define FPGA_PCIX_ADDR_STAT 0xA0C
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/* FPGA master interrupt Cause/Enable bits */
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#define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x1
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#define FPGA_PCIX_INTERRUPT_SGE_DATA 0x2
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#define FPGA_PCIX_INTERRUPT_TP 0x4
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#define FPGA_PCIX_INTERRUPT_MC3 0x8
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#define FPGA_PCIX_INTERRUPT_GMAC 0x10
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#define FPGA_PCIX_INTERRUPT_PCIX 0x20
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/* TP interrupt register addresses */
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#define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10
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#define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA14
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#define FPGA_TP_ADDR_VERSION 0xA18
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/* TP interrupt Cause/Enable bits */
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#define FPGA_TP_INTERRUPT_MC4 0x1
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#define FPGA_TP_INTERRUPT_MC5 0x2
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/*
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* PM interrupt register addresses
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*/
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#define FPGA_MC3_REG_INTRENABLE 0xA20
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#define FPGA_MC3_REG_INTRCAUSE 0xA24
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#define FPGA_MC3_REG_VERSION 0xA28
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/*
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* GMAC interrupt register addresses
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*/
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#define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA30
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#define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA34
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#define FPGA_GMAC_ADDR_VERSION 0xA38
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/* GMAC Cause/Enable bits */
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#define FPGA_GMAC_INTERRUPT_PORT0 0x1
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#define FPGA_GMAC_INTERRUPT_PORT1 0x2
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#define FPGA_GMAC_INTERRUPT_PORT2 0x4
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#define FPGA_GMAC_INTERRUPT_PORT3 0x8
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/* MI0 registers */
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#define A_MI0_CLK 0xb00
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#define S_MI0_CLK_DIV 0
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#define M_MI0_CLK_DIV 0xff
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#define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV)
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#define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV)
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#define S_MI0_CLK_CNT 8
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#define M_MI0_CLK_CNT 0xff
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#define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT)
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#define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT)
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#define A_MI0_CSR 0xb04
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#define S_MI0_CSR_POLL 0
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#define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL)
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#define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U)
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#define S_MI0_PREAMBLE 1
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#define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE)
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#define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U)
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#define S_MI0_INTR_ENABLE 2
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#define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE)
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#define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U)
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#define S_MI0_BUSY 3
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#define V_MI0_BUSY(x) ((x) << S_MI0_BUSY)
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#define F_MI0_BUSY V_MI0_BUSY(1U)
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#define S_MI0_MDIO 4
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#define V_MI0_MDIO(x) ((x) << S_MI0_MDIO)
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#define F_MI0_MDIO V_MI0_MDIO(1U)
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#define A_MI0_ADDR 0xb08
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#define S_MI0_PHY_REG_ADDR 0
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#define M_MI0_PHY_REG_ADDR 0x1f
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#define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR)
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#define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR)
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#define S_MI0_PHY_ADDR 5
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#define M_MI0_PHY_ADDR 0x1f
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#define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR)
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#define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR)
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#define A_MI0_DATA_EXT 0xb0c
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#define A_MI0_DATA_INT 0xb10
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/* GMAC registers */
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#define A_GMAC_MACID_LO 0x28
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#define A_GMAC_MACID_HI 0x2c
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#define A_GMAC_CSR 0x30
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#define S_INTERFACE 0
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#define M_INTERFACE 0x3
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#define V_INTERFACE(x) ((x) << S_INTERFACE)
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#define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
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#define S_MAC_TX_ENABLE 2
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#define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE)
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#define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U)
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#define S_MAC_RX_ENABLE 3
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#define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE)
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#define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U)
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#define S_MAC_LB_ENABLE 4
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#define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE)
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#define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U)
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#define S_MAC_SPEED 5
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#define M_MAC_SPEED 0x3
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#define V_MAC_SPEED(x) ((x) << S_MAC_SPEED)
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#define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED)
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#define S_MAC_HD_FC_ENABLE 7
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#define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE)
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#define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U)
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#define S_MAC_HALF_DUPLEX 8
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#define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX)
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#define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U)
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#define S_MAC_PROMISC 9
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#define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC)
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#define F_MAC_PROMISC V_MAC_PROMISC(1U)
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#define S_MAC_MC_ENABLE 10
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#define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE)
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#define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U)
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#define S_MAC_RESET 11
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#define V_MAC_RESET(x) ((x) << S_MAC_RESET)
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#define F_MAC_RESET V_MAC_RESET(1U)
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#define S_MAC_RX_PAUSE_ENABLE 12
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#define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE)
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#define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U)
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#define S_MAC_TX_PAUSE_ENABLE 13
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#define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE)
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#define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U)
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#define S_MAC_LWM_ENABLE 14
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#define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE)
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#define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U)
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#define S_MAC_MAGIC_PKT_ENABLE 15
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#define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE)
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#define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U)
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#define S_MAC_ISL_ENABLE 16
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#define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE)
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#define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U)
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#define S_MAC_JUMBO_ENABLE 17
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#define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE)
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#define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U)
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#define S_MAC_RX_PAD_ENABLE 18
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#define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE)
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#define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U)
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#define S_MAC_RX_CRC_ENABLE 19
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#define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE)
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#define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U)
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#define A_GMAC_IFS 0x34
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#define S_MAC_IFS2 0
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#define M_MAC_IFS2 0x3f
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#define V_MAC_IFS2(x) ((x) << S_MAC_IFS2)
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#define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2)
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#define S_MAC_IFS1 8
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#define M_MAC_IFS1 0x7f
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#define V_MAC_IFS1(x) ((x) << S_MAC_IFS1)
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#define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1)
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#define A_GMAC_JUMBO_FRAME_LEN 0x38
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#define A_GMAC_LNK_DLY 0x3c
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#define A_GMAC_PAUSETIME 0x40
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#define A_GMAC_MCAST_LO 0x44
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#define A_GMAC_MCAST_HI 0x48
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#define A_GMAC_MCAST_MASK_LO 0x4c
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#define A_GMAC_MCAST_MASK_HI 0x50
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#define A_GMAC_RMT_CNT 0x54
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#define A_GMAC_RMT_DATA 0x58
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#define A_GMAC_BACKOFF_SEED 0x5c
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#define A_GMAC_TXF_THRES 0x60
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#define S_TXF_READ_THRESHOLD 0
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#define M_TXF_READ_THRESHOLD 0xff
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#define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD)
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#define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD)
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#define S_TXF_WRITE_THRESHOLD 16
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#define M_TXF_WRITE_THRESHOLD 0xff
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#define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD)
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#define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD)
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#define MAC_REG_BASE 0x600
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#define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg))
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#define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO)
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#define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI)
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#define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR)
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#define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS)
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#define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN)
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#define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY)
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#define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME)
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#define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO)
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#define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI)
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#define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO)
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#define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI)
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#define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT)
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#define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA)
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#define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED)
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#define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES)
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#endif
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