/*****************************************************************************
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* *
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* File: common.h *
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* $Revision: 1.21 $ *
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* $Date: 2005/06/22 00:43:25 $ *
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* Description: *
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* part of the Chelsio 10Gb Ethernet Driver. *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License, version 2, as *
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* published by the Free Software Foundation. *
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* *
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* You should have received a copy of the GNU General Public License along *
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* with this program; if not, see <http://www.gnu.org/licenses/>. *
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* *
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
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* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
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* *
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* http://www.chelsio.com *
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* *
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* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
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* All rights reserved. *
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* *
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* Maintainers: maintainers@chelsio.com *
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* *
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* Authors: Dimitrios Michailidis <dm@chelsio.com> *
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* Tina Yang <tainay@chelsio.com> *
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* Felix Marti <felix@chelsio.com> *
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* Scott Bardone <sbardone@chelsio.com> *
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* Kurt Ottaway <kottaway@chelsio.com> *
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* Frank DiMambro <frank@chelsio.com> *
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* *
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* History: *
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* *
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****************************************************************************/
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#define pr_fmt(fmt) "cxgb: " fmt
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#ifndef _CXGB_COMMON_H_
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#define _CXGB_COMMON_H_
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/ethtool.h>
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#include <linux/if_vlan.h>
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#include <linux/mdio.h>
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#include <linux/crc32.h>
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#include <linux/slab.h>
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#include <asm/io.h>
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#include <linux/pci_ids.h>
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#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
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#define DRV_NAME "cxgb"
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#define CH_DEVICE(devid, ssid, idx) \
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{ PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
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#define SUPPORTED_PAUSE (1 << 13)
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#define SUPPORTED_LOOPBACK (1 << 15)
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#define ADVERTISED_PAUSE (1 << 13)
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#define ADVERTISED_ASYM_PAUSE (1 << 14)
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typedef struct adapter adapter_t;
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struct t1_rx_mode {
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struct net_device *dev;
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};
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#define t1_rx_mode_promisc(rm) (rm->dev->flags & IFF_PROMISC)
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#define t1_rx_mode_allmulti(rm) (rm->dev->flags & IFF_ALLMULTI)
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#define t1_rx_mode_mc_cnt(rm) (netdev_mc_count(rm->dev))
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#define t1_get_netdev(rm) (rm->dev)
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#define MAX_NPORTS 4
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#define PORT_MASK ((1 << MAX_NPORTS) - 1)
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#define NMTUS 8
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#define TCB_SIZE 128
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#define SPEED_INVALID 0xffff
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#define DUPLEX_INVALID 0xff
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/* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
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#define PM3393_MAX_FRAME_SIZE 9600
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#define VSC7326_MAX_MTU 9600
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enum {
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CHBT_BOARD_N110,
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CHBT_BOARD_N210,
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CHBT_BOARD_7500,
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CHBT_BOARD_8000,
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CHBT_BOARD_CHT101,
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CHBT_BOARD_CHT110,
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CHBT_BOARD_CHT210,
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CHBT_BOARD_CHT204,
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CHBT_BOARD_CHT204V,
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CHBT_BOARD_CHT204E,
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CHBT_BOARD_CHN204,
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CHBT_BOARD_COUGAR,
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CHBT_BOARD_6800,
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CHBT_BOARD_SIMUL,
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};
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enum {
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CHBT_TERM_FPGA,
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CHBT_TERM_T1,
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CHBT_TERM_T2,
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CHBT_TERM_T3
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};
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enum {
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CHBT_MAC_CHELSIO_A,
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CHBT_MAC_IXF1010,
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CHBT_MAC_PM3393,
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CHBT_MAC_VSC7321,
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CHBT_MAC_DUMMY
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};
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enum {
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CHBT_PHY_88E1041,
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CHBT_PHY_88E1111,
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CHBT_PHY_88X2010,
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CHBT_PHY_XPAK,
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CHBT_PHY_MY3126,
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CHBT_PHY_8244,
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CHBT_PHY_DUMMY
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};
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enum {
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PAUSE_RX = 1 << 0,
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PAUSE_TX = 1 << 1,
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PAUSE_AUTONEG = 1 << 2
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};
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/* Revisions of T1 chip */
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enum {
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TERM_T1A = 0,
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TERM_T1B = 1,
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TERM_T2 = 3
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};
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struct sge_params {
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unsigned int cmdQ_size[2];
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unsigned int freelQ_size[2];
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unsigned int large_buf_capacity;
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unsigned int rx_coalesce_usecs;
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unsigned int last_rx_coalesce_raw;
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unsigned int default_rx_coalesce_usecs;
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unsigned int sample_interval_usecs;
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unsigned int coalesce_enable;
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unsigned int polling;
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};
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struct chelsio_pci_params {
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unsigned short speed;
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unsigned char width;
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unsigned char is_pcix;
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};
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struct tp_params {
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unsigned int pm_size;
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unsigned int cm_size;
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unsigned int pm_rx_base;
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unsigned int pm_tx_base;
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unsigned int pm_rx_pg_size;
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unsigned int pm_tx_pg_size;
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unsigned int pm_rx_num_pgs;
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unsigned int pm_tx_num_pgs;
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unsigned int rx_coalescing_size;
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unsigned int use_5tuple_mode;
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};
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struct mc5_params {
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unsigned int mode; /* selects MC5 width */
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unsigned int nservers; /* size of server region */
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unsigned int nroutes; /* size of routing region */
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};
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/* Default MC5 region sizes */
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#define DEFAULT_SERVER_REGION_LEN 256
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#define DEFAULT_RT_REGION_LEN 1024
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struct adapter_params {
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struct sge_params sge;
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struct mc5_params mc5;
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struct tp_params tp;
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struct chelsio_pci_params pci;
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const struct board_info *brd_info;
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unsigned short mtus[NMTUS];
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unsigned int nports; /* # of ethernet ports */
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unsigned int stats_update_period;
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unsigned short chip_revision;
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unsigned char chip_version;
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unsigned char is_asic;
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unsigned char has_msi;
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};
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struct link_config {
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unsigned int supported; /* link capabilities */
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unsigned int advertising; /* advertised capabilities */
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unsigned short requested_speed; /* speed user has requested */
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unsigned short speed; /* actual link speed */
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unsigned char requested_duplex; /* duplex user has requested */
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unsigned char duplex; /* actual link duplex */
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unsigned char requested_fc; /* flow control user has requested */
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unsigned char fc; /* actual link flow control */
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unsigned char autoneg; /* autonegotiating? */
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};
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struct cmac;
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struct cphy;
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struct port_info {
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struct net_device *dev;
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struct cmac *mac;
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struct cphy *phy;
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struct link_config link_config;
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};
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struct sge;
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struct peespi;
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struct adapter {
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u8 __iomem *regs;
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struct pci_dev *pdev;
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unsigned long registered_device_map;
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unsigned long open_device_map;
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unsigned long flags;
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const char *name;
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int msg_enable;
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u32 mmio_len;
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struct work_struct ext_intr_handler_task;
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struct adapter_params params;
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/* Terminator modules. */
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struct sge *sge;
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struct peespi *espi;
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struct petp *tp;
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struct napi_struct napi;
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struct port_info port[MAX_NPORTS];
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struct delayed_work stats_update_task;
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struct timer_list stats_update_timer;
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spinlock_t tpi_lock;
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spinlock_t work_lock;
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spinlock_t mac_lock;
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/* guards async operations */
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spinlock_t async_lock ____cacheline_aligned;
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u32 slow_intr_mask;
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int t1powersave;
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};
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enum { /* adapter flags */
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FULL_INIT_DONE = 1 << 0,
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};
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struct mdio_ops;
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struct gmac;
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struct gphy;
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struct board_info {
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unsigned char board;
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unsigned char port_number;
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unsigned long caps;
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unsigned char chip_term;
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unsigned char chip_mac;
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unsigned char chip_phy;
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unsigned int clock_core;
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unsigned int clock_mc3;
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unsigned int clock_mc4;
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unsigned int espi_nports;
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unsigned int clock_elmer0;
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unsigned char mdio_mdien;
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unsigned char mdio_mdiinv;
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unsigned char mdio_mdc;
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unsigned char mdio_phybaseaddr;
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const struct gmac *gmac;
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const struct gphy *gphy;
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const struct mdio_ops *mdio_ops;
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const char *desc;
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};
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static inline int t1_is_asic(const adapter_t *adapter)
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{
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return adapter->params.is_asic;
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}
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extern const struct pci_device_id t1_pci_tbl[];
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static inline int adapter_matches_type(const adapter_t *adapter,
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int version, int revision)
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{
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return adapter->params.chip_version == version &&
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adapter->params.chip_revision == revision;
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}
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#define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
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#define is_T2(adap) adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
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/* Returns true if an adapter supports VLAN acceleration and TSO */
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static inline int vlan_tso_capable(const adapter_t *adapter)
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{
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return !t1_is_T1B(adapter);
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}
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#define for_each_port(adapter, iter) \
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for (iter = 0; iter < (adapter)->params.nports; ++iter)
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#define board_info(adapter) ((adapter)->params.brd_info)
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#define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
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static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
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{
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return board_info(adap)->clock_core / 1000000;
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}
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int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
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int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
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int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
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int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
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void t1_interrupts_enable(adapter_t *adapter);
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void t1_interrupts_disable(adapter_t *adapter);
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void t1_interrupts_clear(adapter_t *adapter);
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int t1_elmer0_ext_intr_handler(adapter_t *adapter);
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void t1_elmer0_ext_intr(adapter_t *adapter);
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int t1_slow_intr_handler(adapter_t *adapter);
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int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
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const struct board_info *t1_get_board_info(unsigned int board_id);
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const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
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unsigned short ssid);
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int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data);
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int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
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struct adapter_params *p);
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int t1_init_hw_modules(adapter_t *adapter);
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int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
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void t1_free_sw_modules(adapter_t *adapter);
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void t1_fatal_err(adapter_t *adapter);
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void t1_link_changed(adapter_t *adapter, int port_id);
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void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
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int speed, int duplex, int pause);
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#endif /* _CXGB_COMMON_H_ */
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