/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2016 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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**********************************************************************/
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include "liquidio_common.h"
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#include "octeon_droq.h"
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#include "octeon_iq.h"
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#include "response_manager.h"
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#include "octeon_device.h"
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#include "octeon_main.h"
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static void oct_poll_req_completion(struct work_struct *work);
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int octeon_setup_response_list(struct octeon_device *oct)
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{
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int i, ret = 0;
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struct cavium_wq *cwq;
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for (i = 0; i < MAX_RESPONSE_LISTS; i++) {
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INIT_LIST_HEAD(&oct->response_list[i].head);
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spin_lock_init(&oct->response_list[i].lock);
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atomic_set(&oct->response_list[i].pending_req_count, 0);
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}
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spin_lock_init(&oct->cmd_resp_wqlock);
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oct->dma_comp_wq.wq = alloc_workqueue("dma-comp", WQ_MEM_RECLAIM, 0);
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if (!oct->dma_comp_wq.wq) {
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dev_err(&oct->pci_dev->dev, "failed to create wq thread\n");
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return -ENOMEM;
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}
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cwq = &oct->dma_comp_wq;
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INIT_DELAYED_WORK(&cwq->wk.work, oct_poll_req_completion);
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cwq->wk.ctxptr = oct;
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oct->cmd_resp_state = OCT_DRV_ONLINE;
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return ret;
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}
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void octeon_delete_response_list(struct octeon_device *oct)
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{
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cancel_delayed_work_sync(&oct->dma_comp_wq.wk.work);
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destroy_workqueue(oct->dma_comp_wq.wq);
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}
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int lio_process_ordered_list(struct octeon_device *octeon_dev,
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u32 force_quit)
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{
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struct octeon_response_list *ordered_sc_list;
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struct octeon_soft_command *sc;
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int request_complete = 0;
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int resp_to_process = MAX_ORD_REQS_TO_PROCESS;
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u32 status;
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u64 status64;
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octeon_free_sc_done_list(octeon_dev);
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ordered_sc_list = &octeon_dev->response_list[OCTEON_ORDERED_SC_LIST];
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do {
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spin_lock_bh(&ordered_sc_list->lock);
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if (list_empty(&ordered_sc_list->head)) {
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spin_unlock_bh(&ordered_sc_list->lock);
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return 1;
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}
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sc = list_first_entry(&ordered_sc_list->head,
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struct octeon_soft_command, node);
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status = OCTEON_REQUEST_PENDING;
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/* check if octeon has finished DMA'ing a response
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* to where rptr is pointing to
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*/
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status64 = *sc->status_word;
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if (status64 != COMPLETION_WORD_INIT) {
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/* This logic ensures that all 64b have been written.
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* 1. check byte 0 for non-FF
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* 2. if non-FF, then swap result from BE to host order
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* 3. check byte 7 (swapped to 0) for non-FF
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* 4. if non-FF, use the low 32-bit status code
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* 5. if either byte 0 or byte 7 is FF, don't use status
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*/
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if ((status64 & 0xff) != 0xff) {
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octeon_swap_8B_data(&status64, 1);
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if (((status64 & 0xff) != 0xff)) {
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/* retrieve 16-bit firmware status */
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status = (u32)(status64 & 0xffffULL);
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if (status) {
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status =
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FIRMWARE_STATUS_CODE(status);
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} else {
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/* i.e. no error */
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status = OCTEON_REQUEST_DONE;
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}
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}
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}
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} else if (unlikely(force_quit) || (sc->expiry_time &&
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time_after(jiffies, (unsigned long)sc->expiry_time))) {
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struct octeon_instr_irh *irh =
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(struct octeon_instr_irh *)&sc->cmd.cmd3.irh;
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dev_err(&octeon_dev->pci_dev->dev, "%s: ", __func__);
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dev_err(&octeon_dev->pci_dev->dev,
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"cmd %x/%x/%llx/%llx failed, ",
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irh->opcode, irh->subcode,
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sc->cmd.cmd3.ossp[0], sc->cmd.cmd3.ossp[1]);
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dev_err(&octeon_dev->pci_dev->dev,
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"timeout (%ld, %ld)\n",
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(long)jiffies, (long)sc->expiry_time);
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status = OCTEON_REQUEST_TIMEOUT;
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}
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if (status != OCTEON_REQUEST_PENDING) {
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sc->sc_status = status;
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/* we have received a response or we have timed out */
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/* remove node from linked list */
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list_del(&sc->node);
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atomic_dec(&octeon_dev->response_list
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[OCTEON_ORDERED_SC_LIST].
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pending_req_count);
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if (!sc->callback) {
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atomic_inc(&octeon_dev->response_list
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[OCTEON_DONE_SC_LIST].
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pending_req_count);
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list_add_tail(&sc->node,
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&octeon_dev->response_list
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[OCTEON_DONE_SC_LIST].head);
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if (unlikely(READ_ONCE(sc->caller_is_done))) {
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/* caller does not wait for response
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* from firmware
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*/
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if (status != OCTEON_REQUEST_DONE) {
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struct octeon_instr_irh *irh;
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irh =
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(struct octeon_instr_irh *)
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&sc->cmd.cmd3.irh;
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dev_dbg
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(&octeon_dev->pci_dev->dev,
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"%s: sc failed: opcode=%x, ",
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__func__, irh->opcode);
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dev_dbg
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(&octeon_dev->pci_dev->dev,
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"subcode=%x, ossp[0]=%llx, ",
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irh->subcode,
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sc->cmd.cmd3.ossp[0]);
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dev_dbg
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(&octeon_dev->pci_dev->dev,
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"ossp[1]=%llx, status=%d\n",
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sc->cmd.cmd3.ossp[1],
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status);
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}
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} else {
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complete(&sc->complete);
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}
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spin_unlock_bh(&ordered_sc_list->lock);
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} else {
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/* sc with callback function */
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if (status == OCTEON_REQUEST_TIMEOUT) {
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atomic_inc(&octeon_dev->response_list
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[OCTEON_ZOMBIE_SC_LIST].
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pending_req_count);
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list_add_tail(&sc->node,
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&octeon_dev->response_list
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[OCTEON_ZOMBIE_SC_LIST].
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head);
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}
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spin_unlock_bh(&ordered_sc_list->lock);
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sc->callback(octeon_dev, status,
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sc->callback_arg);
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/* sc is freed by caller */
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}
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request_complete++;
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} else {
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/* no response yet */
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request_complete = 0;
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spin_unlock_bh
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(&ordered_sc_list->lock);
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}
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/* If we hit the Max Ordered requests to process every loop,
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* we quit
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* and let this function be invoked the next time the poll
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* thread runs
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* to process the remaining requests. This function can take up
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* the entire CPU if there is no upper limit to the requests
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* processed.
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*/
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if (request_complete >= resp_to_process)
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break;
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} while (request_complete);
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return 0;
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}
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static void oct_poll_req_completion(struct work_struct *work)
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{
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struct cavium_wk *wk = (struct cavium_wk *)work;
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struct octeon_device *oct = (struct octeon_device *)wk->ctxptr;
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struct cavium_wq *cwq = &oct->dma_comp_wq;
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lio_process_ordered_list(oct, 0);
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if (atomic_read(&oct->response_list
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[OCTEON_ORDERED_SC_LIST].pending_req_count))
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queue_delayed_work(cwq->wq, &cwq->wk.work, msecs_to_jiffies(1));
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}
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